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Subject: Re: [PATCH] x86/mm/sme: Fix definition of PMD_FLAGS_DEC_WP
To:     Arvind Sankar <nivedita@alum.mit.edu>,
        Dave Hansen <dave.hansen@linux.intel.com>,
        Andy Lutomirski <luto@kernel.org>,
        Peter Zijlstra <peterz@infradead.org>
Cc:     x86@kernel.org, linux-kernel@vger.kernel.org,
        Borislav Petkov <bp@alien8.de>
References: <3960752c-af6c-e7ef-1acc-c7df8f60cf48@amd.com>
 <20201109173543.551282-1-nivedita@alum.mit.edu>
From:   Tom Lendacky <thomas.lendacky@amd.com>
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Date:   Mon, 9 Nov 2020 14:41:48 -0600
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On 11/9/20 11:35 AM, Arvind Sankar wrote:
> The PAT bit is in different locations for 4k and 2M/1G page table
> entries.
> 
> Add a definition for _PAGE_LARGE_CACHE_MASK to represent the three
> caching bits (PWT, PCD, PAT), similar to _PAGE_CACHE_MASK for 4k pages,
> and use it in the definition of PMD_FLAGS_DEC_WP to get the correct PAT
> index for write-protected pages.
> 
> Remove a duplication definition of _PAGE_PAT_LARGE.
> 
> Signed-off-by: Arvind Sankar <nivedita@alum.mit.edu>

Fixes: tag?

Tested-by: Tom Lendacky <thomas.lendacky@amd.com>

> ---
>  arch/x86/include/asm/pgtable_types.h | 3 +--
>  arch/x86/mm/mem_encrypt_identity.c   | 4 ++--
>  2 files changed, 3 insertions(+), 4 deletions(-)
>