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Date:   Mon, 9 Nov 2020 21:15:15 +0000
From:   Mark Brown <broonie@kernel.org>
To:     =?iso-8859-1?Q?Cl=E9ment_P=E9ron?= <peron.clem@gmail.com>
Cc:     Rob Herring <robh+dt@kernel.org>,
        Maxime Ripard <mripard@kernel.org>,
        Jernej =?utf-8?Q?=C5=A0krabec?= <jernej.skrabec@siol.net>,
        Chen-Yu Tsai <wens@csie.org>,
        Liam Girdwood <lgirdwood@gmail.com>,
        Jaroslav Kysela <perex@perex.cz>,
        Takashi Iwai <tiwai@suse.com>,
        Marcus Cooper <codekipper@gmail.com>,
        Linux-ALSA <alsa-devel@alsa-project.org>,
        devicetree <devicetree@vger.kernel.org>,
        linux-arm-kernel <linux-arm-kernel@lists.infradead.org>,
        linux-kernel <linux-kernel@vger.kernel.org>,
        Samuel Holland <samuel@sholland.org>
Subject: Re: ASoC: Question regarding device-tree multi-lane I2S for
 Allwinner SoC
Message-ID: <20201109211515.GO6380@sirena.org.uk>
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On Sun, Nov 01, 2020 at 06:30:15PM +0100, Cl=E9ment P=E9ron wrote:

Sorry about the delay here.

>     dai-tdm-slot-tx-mask-0 =3D <1 1>;
>     dai-tdm-slot-tx-mask-1 =3D <1 1>;
>     dai-tdm-slot-tx-mask-2 =3D <1 1>;
>     dai-tdm-slot-tx-mask-3 =3D <1 1>;

=2E..

> This kind of representation gives the information that 2 slots should
> be enabled as TX per lane but don't give which slot to map.

The way the above should be interpreted is as a bitmask of slots to use,
I'm hoping that the above is for a system with 4 TX data wires each
using two slots (such designs get used for things like surround sound
amps). =20

> I was thinking about a representation per lane but maybe it's a bit
> complicated  ?

>     dai-format =3D "dsp_a";
>     dai-tdm-slot-width =3D <32>;
>     // Lane 0 : Output 8 channels 0-7 using TDM
>     dai-tdm-slot-tx-mask-0 =3D <1 1 1 1 1 1 1 1>;
>     dai-tdm-slot-chmap-0 =3D <0 1 2 3 4 5 6 7>;
>     // Lane 1 : Output 3 channels 5-7 using TDM
>     dai-tdm-slot-tx-mask-1 =3D <1 1 1>;
>     dai-tdm-slot-chmap-1 =3D <5 6 7>;

I'd expect lane 1 to end up as

     dai-tdm-slot-tx-mask-1 =3D < 0 0 0 0 0 1 1 1 >;

>     // Lane 0 : Output channels 0,1
>     dai-tdm-slot-tx-mask-0 =3D <1 1>;
>     dai-tdm-slot-chmap-0 =3D <0 1>;
>     // Lane 1: Output channels 2,3
>     dai-tdm-slot-tx-mask-1 =3D <1 1>;
>     dai-tdm-slot-chmap-1 =3D <2 3>;
>     // Lane 2: Output channels 4,5
>     dai-tdm-slot-tx-mask-2 =3D <1 1>;
>     dai-tdm-slot-chmap-2 =3D <4 5>;
>     // Lane 3: Output channels 6,7
>     dai-tdm-slot-tx-mask-3 =3D <1 1>;
>     dai-tdm-slot-chmap-3 =3D <6 7>;

> What do you think? Do you have any remark / idea about this ?

I can see the use for the chmap binding, I can see that we might have a
system which has for example outputs labelled in some unusual order and
we'd want to remap them.  I'm less sure about defining a channel map in
a way that changes the meaning of the masks though, that seems like it'd
lead to incompatibilities.  How about making chmap also an array like
the mask is with the bits set in the mask indicating which slots in the
chmap are valid, that way your -3 would end up as:

      dai-tdm-slot-tx-mask-3 =3D <0 0 0 0 0 0 0 1 1>;
      dai-tdm-slot-chmap-3   =3D <0 0 0 0 0 0 0 6 7>;

and something that only understands the mask would at least get the
correct channels even if in a jumbled order?

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