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[23.128.96.18]) by mx.google.com with ESMTP id cb12si5873314edb.272.2020.11.09.20.25.20; Mon, 09 Nov 2020 20:25:43 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@broadcom.com header.s=google header.b=iCh4cTNR; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=broadcom.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731631AbgKJEX6 (ORCPT + 99 others); Mon, 9 Nov 2020 23:23:58 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51592 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731400AbgKJEX5 (ORCPT ); Mon, 9 Nov 2020 23:23:57 -0500 Received: from mail-lf1-x142.google.com (mail-lf1-x142.google.com [IPv6:2a00:1450:4864:20::142]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 888D8C0613CF for ; Mon, 9 Nov 2020 20:23:56 -0800 (PST) Received: by mail-lf1-x142.google.com with SMTP id l2so15651843lfk.0 for ; Mon, 09 Nov 2020 20:23:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=broadcom.com; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=z/fsyWPbY03wZJ3A/BbF8ha4DatLv2QBLhJDrPA0RNE=; b=iCh4cTNRnbFIE1GZaQLfDr4TGyM6CeVBaR3Lu9cxvNxQRm6wF9dG3hHazEKBZbkksV PDCniJzGzi+QdBNb2e1hwJbTjbF4aCpTeLyHKWkaAldTQca80ykJDmHq8Ty+R1ZD04/6 bclUb/vXUqXDjXKQcSfgAQQs6gtYpEBkT77ZY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=z/fsyWPbY03wZJ3A/BbF8ha4DatLv2QBLhJDrPA0RNE=; b=mlQonQSek6VCJ1EJa1V08okbZkf2ICtwkAJnsAro7iO3+kOCCEVP6hakiBsKY3pl4o PZuvZoDnOBGwu7LNhncP8ETlcG6kRb7KwZtsYJGicmldwpk/+SX0QESQm5/wTwLMggr/ WMMyLsPncJzSjAoOWdQEi9C6Iw4uRNp9t3/Vm8phmr33NKDIPlznQhI5F4JU2WmwBFay EDgU8qSKSxS/gBBiHTCMMCjjtH7XXFNJvMXz9Ncb+/2PkqoVWVb5aI+BsZwj5VGjpkzJ 8sBqGfAKLSD/OZOcvBJPAUZIEL39QZaXu6D46mn9rXVzkZV/X1oL4qlIJK6aZWCObEoY eSRQ== X-Gm-Message-State: AOAM531V4opZQITxTXiCD9icVHwJfO+OH4Dw2DEgG3WpvXSHa1V2sAId OIA2Z6hRlRGjcbJxi10WsjjzGVYBOOVf4j6Uwyipag== X-Received: by 2002:a19:4f47:: with SMTP id a7mr7360366lfk.245.1604982234320; Mon, 09 Nov 2020 20:23:54 -0800 (PST) MIME-Version: 1.0 References: <1604684486-16272-1-git-send-email-dphadke@linux.microsoft.com> In-Reply-To: <1604684486-16272-1-git-send-email-dphadke@linux.microsoft.com> From: Rayagonda Kokatanur Date: Tue, 10 Nov 2020 09:53:41 +0530 Message-ID: Subject: Re: [PATCH v3 5/6] i2c: iproc: handle master read request To: Ray Jui Cc: Andy Shevchenko , BCM Kernel Feedback , Brendan Higgins , Dhananjay Phadke , Florian Fainelli , linux-arm Mailing List , linux-i2c , Linux Kernel Mailing List , Lori Hikichi , Ray Jui , Scott Branden , Wolfram Sang Content-Type: multipart/signed; protocol="application/pkcs7-signature"; micalg=sha-256; boundary="000000000000fb6d4505b3b90b6e" Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org --000000000000fb6d4505b3b90b6e Content-Type: text/plain; charset="UTF-8" Hi Ray, Could you please check Dhananjay comments and update your thoughts. On Fri, Nov 6, 2020 at 11:11 PM Dhananjay Phadke wrote: > > On Thu, 5 Nov 2020 15:13:04 +0530, Rayagonda Kokatanur wrote: > >> So the suggestion was to set HW threshold for rx fifo interrupt, not > >> really a SW property. By setting it in DT, makes it easier to > >> customize for target system, module param needs or ioctl makes it > >> dependent on userpsace to configure it. > >> > >> The need for tasklet seems to arise from the fact that many bytes are > >> left in the fifo. If there's a common problem here, such tasklet would be > >> needed in i2c subsys rather than controller specific tweak, akin to > >> how networking uses NAPI or adding block transactions to the interface? > >> > >> For master write-read event, it seems both IS_S_RD_EVENT_SHIFT and > >> IS_S_RX_EVENT_SHIFT are detected, which implies that core is late to > >> drain rx fifo i.e. write is complete and the read has started on the bus? > > > >Yes it's true that for master write-read events both > >IS_S_RD_EVENT_SHIFT and IS_S_RX_EVENT_SHIFT are coming together. > >So before the slave starts transmitting data to the master, it should > >first read all data from rx-fifo i.e. complete master write and then > >process master read. > > > >To minimise interrupt overhead, we are batching 64bytes. > >To keep isr running for less time, we are using a tasklet. > >Again to keep the tasklet not running for more than 20u, we have set > >max of 10 bytes data read from rx-fifo per tasklet run. > > > >If we start processing everything in isr and using rx threshold > >interrupt, then isr will run for a longer time and this may hog the > >system. > >For example, to process 10 bytes it takes 20us, to process 30 bytes it > >takes 60us and so on. > >So is it okay to run isr for so long ? > > > >Keeping all this in mind we thought a tasklet would be a good option > >and kept max of 10 bytes read per tasklet. > > > >Please let me know if you still feel we should not use a tasklet and > >don't batch 64 bytes. > > Deferring to tasklet is OK, could use a kernel thread (i.e. threaded_irq) > as i2c rate is quite low. > > But do enable rx_threshold and read out early. This will avoid fifo full > or master write-read situation where lot of bytes must be drained from rx > fifo before serving tx fifo (avoid tx underrun). > > Best would have been setting up DMA into mem (some controllers seem capable). > In absence of that, it's a trade off: if rx intr threshold is low, > there will be more interrupts, but less time spent in each. Default could > still be 64B or no-thresh (allow override in dtb). > > Few other comments - > > >+ /* schedule tasklet to read data later */ > >+ tasklet_schedule(&iproc_i2c->slave_rx_tasklet); > >+ > >+ /* clear only IS_S_RX_EVENT_SHIFT interrupt */ > >+ iproc_i2c_wr_reg(iproc_i2c, IS_OFFSET, > >+ BIT(IS_S_RX_EVENT_SHIFT)); > >+ } > > Why clearing one rx interrupt bit here after scheduling tasklet? Should all that > be done by tasklet? Also should just return after scheduling tasklet? > > Thanks, > Dhananjay --000000000000fb6d4505b3b90b6e Content-Type: application/pkcs7-signature; name="smime.p7s" Content-Transfer-Encoding: base64 Content-Disposition: attachment; filename="smime.p7s" Content-Description: S/MIME Cryptographic Signature MIIQVwYJKoZIhvcNAQcCoIIQSDCCEEQCAQExDzANBglghkgBZQMEAgEFADALBgkqhkiG9w0BBwGg gg2sMIIE6DCCA9CgAwIBAgIOSBtqCRO9gCTKXSLwFPMwDQYJKoZIhvcNAQELBQAwTDEgMB4GA1UE CxMXR2xvYmFsU2lnbiBSb290IENBIC0gUjMxEzARBgNVBAoTCkdsb2JhbFNpZ24xEzARBgNVBAMT Ckdsb2JhbFNpZ24wHhcNMTYwNjE1MDAwMDAwWhcNMjQwNjE1MDAwMDAwWjBdMQswCQYDVQQGEwJC RTEZMBcGA1UEChMQR2xvYmFsU2lnbiBudi1zYTEzMDEGA1UEAxMqR2xvYmFsU2lnbiBQZXJzb25h bFNpZ24gMiBDQSAtIFNIQTI1NiAtIEczMIIBIjANBgkqhkiG9w0BAQEFAAOCAQ8AMIIBCgKCAQEA tpZok2X9LAHsYqMNVL+Ly6RDkaKar7GD8rVtb9nw6tzPFnvXGeOEA4X5xh9wjx9sScVpGR5wkTg1 fgJIXTlrGESmaqXIdPRd9YQ+Yx9xRIIIPu3Jp/bpbiZBKYDJSbr/2Xago7sb9nnfSyjTSnucUcIP ZVChn6hKneVGBI2DT9yyyD3PmCEJmEzA8Y96qT83JmVH2GaPSSbCw0C+Zj1s/zqtKUbwE5zh8uuZ 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