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Date:   Tue, 10 Nov 2020 19:21:38 +0000
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Subject: Re: [EXTERNAL] [tip: x86/apic] x86/io_apic: Cleanup trigger/polarity helpers
To:     Thomas Gleixner <tglx@linutronix.de>,
        Tom Lendacky <thomas.lendacky@amd.com>,
        Borislav Petkov <bp@alien8.de>
CC:     linux-kernel@vger.kernel.org, x86 <x86@kernel.org>,
        Qian Cai <cai@redhat.com>, Joerg Roedel <joro@8bytes.org>
From:   David Woodhouse <dwmw2@infradead.org>
Message-ID: <45B3C20C-3BBB-40F3-8A7B-EB20EDD0706F@infradead.org>
Precedence: bulk


On 10 November 2020 18:56:17 GMT, Thomas Gleixner <tglx@linutronix=2Ede> w=
rote:
>On Tue, Nov 10 2020 at 18:50, Thomas Gleixner wrote:
>> On Tue, Nov 10 2020 at 16:33, David Woodhouse wrote:
>>> If I could get post-5=2E5 kernels to boot at all with the AMD IOMMU
>>> enabled, I'd have a go at throwing that together now=2E=2E=2E
>>
>> It can share the dmar domain code=2E Let me frob something=2E
>
>Not much to share there and I can't access my AMD machine at the
>moment=2E Something like the untested below should work=2E

Does it even need its own irqdomain? Can it not just allocate directly fro=
m the vector domain then program its own register directly based on the irq=
_cfg?


--=20
Sent from my Android device with K-9 Mail=2E Please excuse my brevity=2E