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Date:   Tue, 10 Nov 2020 21:30:07 +0000
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Subject: Re: [EXTERNAL] [tip: x86/apic] x86/io_apic: Cleanup trigger/polarity helpers
To:     Thomas Gleixner <tglx@linutronix.de>,
        Tom Lendacky <thomas.lendacky@amd.com>,
        Borislav Petkov <bp@alien8.de>
CC:     linux-kernel@vger.kernel.org, x86 <x86@kernel.org>,
        Qian Cai <cai@redhat.com>, Joerg Roedel <joro@8bytes.org>
From:   David Woodhouse <dwmw2@infradead.org>
Message-ID: <8C2E184C-D069-4C60-96B5-0758FBC6E402@infradead.org>
Precedence: bulk


On 10 November 2020 21:01:17 GMT, Thomas Gleixner <tglx@linutronix=2Ede> w=
rote:
>On Tue, Nov 10 2020 at 19:21, David Woodhouse wrote:
>
>> On 10 November 2020 18:56:17 GMT, Thomas Gleixner
><tglx@linutronix=2Ede> wrote:
>>>On Tue, Nov 10 2020 at 18:50, Thomas Gleixner wrote:
>>>> On Tue, Nov 10 2020 at 16:33, David Woodhouse wrote:
>>>>> If I could get post-5=2E5 kernels to boot at all with the AMD IOMMU
>>>>> enabled, I'd have a go at throwing that together now=2E=2E=2E
>>>>
>>>> It can share the dmar domain code=2E Let me frob something=2E
>>>
>>>Not much to share there and I can't access my AMD machine at the
>>>moment=2E Something like the untested below should work=2E
>>
>> Does it even need its own irqdomain? Can it not just allocate
>directly
>> from the vector domain then program its own register directly based
>on
>> the irq_cfg?
>
>It uses pci_enable_msi() and I have no clue about that piece of
>hardware
>and whether that is actually required or not=2E If it is, then it needs a
>domain because that's what pci_enable_msi() uses=2E

I'd be kind of surprised if it is required, but testing on qemu is obvious=
ly not going to cut it=2E Tom?

--=20
Sent from my Android device with K-9 Mail=2E Please excuse my brevity=2E