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From:   "Sia, Jee Heng" <jee.heng.sia@intel.com>
To:     Vinod Koul <vkoul@kernel.org>
CC:     "Eugeniy.Paltsev@synopsys.com" <Eugeniy.Paltsev@synopsys.com>,
        "andriy.shevchenko@linux.intel.com" 
        <andriy.shevchenko@linux.intel.com>,
        "dmaengine@vger.kernel.org" <dmaengine@vger.kernel.org>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
Subject: RE: [PATCH v2 01/15] dt-bindings: dma: Add YAML schemas for
 dw-axi-dmac
Thread-Topic: [PATCH v2 01/15] dt-bindings: dma: Add YAML schemas for
 dw-axi-dmac
Thread-Index: AQHWtnp3naUJQzS9J0iOWt5vJAFyWKnCKP8A
Date:   Wed, 11 Nov 2020 01:36:47 +0000
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References: <20201027063858.4877-1-jee.heng.sia@intel.com>
 <20201027063858.4877-2-jee.heng.sia@intel.com>
 <20201109092640.GB3171@vkoul-mobl>
In-Reply-To: <20201109092640.GB3171@vkoul-mobl>
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> -----Original Message-----
> From: Vinod Koul <vkoul@kernel.org>
> Sent: 09 November 2020 5:27 PM
> To: Sia, Jee Heng <jee.heng.sia@intel.com>
> Cc: Eugeniy.Paltsev@synopsys.com; andriy.shevchenko@linux.intel.com;
> dmaengine@vger.kernel.org; linux-kernel@vger.kernel.org
> Subject: Re: [PATCH v2 01/15] dt-bindings: dma: Add YAML schemas for dw-a=
xi-
> dmac
>=20
> On 27-10-20, 14:38, Sia Jee Heng wrote:
> > YAML schemas Device Tree (DT) binding is the new format for DT to
> > replace the old format. Introduce YAML schemas DT binding for
> > dw-axi-dmac and remove the old version.
>=20
> I see that Rob and DT folks have not been cced, please do so
[>>] ok, I will add them starting v3.
>=20
> >
> > Signed-off-by: Sia Jee Heng <jee.heng.sia@intel.com>
> > ---
> >  .../bindings/dma/snps,dw-axi-dmac.txt         |  39 ------
> >  .../bindings/dma/snps,dw-axi-dmac.yaml        | 124 ++++++++++++++++++
> >  2 files changed, 124 insertions(+), 39 deletions(-)  delete mode
> > 100644 Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.txt
> >  create mode 100644
> > Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml
> >
> > diff --git
> > a/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.txt
> > b/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.txt
> > deleted file mode 100644
> > index dbe160400adc..000000000000
> > --- a/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.txt
> > +++ /dev/null
> > @@ -1,39 +0,0 @@
> > -Synopsys DesignWare AXI DMA Controller
> > -
> > -Required properties:
> > -- compatible: "snps,axi-dma-1.01a"
> > -- reg: Address range of the DMAC registers. This should include
> > -  all of the per-channel registers.
> > -- interrupt: Should contain the DMAC interrupt number.
> > -- dma-channels: Number of channels supported by hardware.
> > -- snps,dma-masters: Number of AXI masters supported by the hardware.
> > -- snps,data-width: Maximum AXI data width supported by hardware.
> > -  (0 - 8bits, 1 - 16bits, 2 - 32bits, ..., 6 - 512bits)
> > -- snps,priority: Priority of channel. Array size is equal to the
> > number of
> > -  dma-channels. Priority value must be programmed within
> > [0:dma-channels-1]
> > -  range. (0 - minimum priority)
> > -- snps,block-size: Maximum block size supported by the controller chan=
nel.
> > -  Array size is equal to the number of dma-channels.
> > -
> > -Optional properties:
> > -- snps,axi-max-burst-len: Restrict master AXI burst length by value
> > specified
> > -  in this property. If this property is missing the maximum AXI burst
> > length
> > -  supported by DMAC is used. [1:256]
> > -
> > -Example:
> > -
> > -dmac: dma-controller@80000 {
> > -	compatible =3D "snps,axi-dma-1.01a";
> > -	reg =3D <0x80000 0x400>;
> > -	clocks =3D <&core_clk>, <&cfgr_clk>;
> > -	clock-names =3D "core-clk", "cfgr-clk";
> > -	interrupt-parent =3D <&intc>;
> > -	interrupts =3D <27>;
> > -
> > -	dma-channels =3D <4>;
> > -	snps,dma-masters =3D <2>;
> > -	snps,data-width =3D <3>;
> > -	snps,block-size =3D <4096 4096 4096 4096>;
> > -	snps,priority =3D <0 1 2 3>;
> > -	snps,axi-max-burst-len =3D <16>;
> > -};
> > diff --git
> > a/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml
> > b/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml
> > new file mode 100644
> > index 000000000000..e688d25864bc
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml
> > @@ -0,0 +1,124 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/dma/snps,dw-axi-dmac.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Synopsys DesignWare AXI DMA Controller
> > +
> > +maintainers:
> > +  - Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com
> > +
> > +description: |
> > + Synopsys DesignWare AXI DMA Controller DT Binding
> > +
> > +properties:
> > +  compatible:
> > +    enum:
> > +      - snps,axi-dma-1.01a
> > +
> > +  reg:
> > +    items:
> > +      - description: Address range of the DMAC registers.
> > +
> > +  reg-names:
> > +    items:
> > +      - const: axidma_ctrl_regs
> > +
> > +  interrupts:
> > +    maxItems: 1
> > +
> > +  clocks:
> > +    items:
> > +      - description: Bus Clock
> > +      - description: Module Clock
> > +
> > +  clock-names:
> > +    items:
> > +      - const: core-clk
> > +      - const: cfgr-clk
> > +
> > +  '#dma-cells':
> > +    const: 1
> > +
> > +  dma-channels:
> > +    description: |
> > +      Number of channels supported by hardware.
> > +
> > +  snps,dma-masters:
> > +    description: |
> > +      Number of AXI masters supported by the hardware.
> > +    allOf:
> > +      - $ref: /schemas/types.yaml#/definitions/uint32
> > +      - enum: [1, 2]
> > +        default: 2
> > +
> > +  snps,data-width:
> > +    description: |
> > +      AXI data width supported by hardware.
> > +      (0 - 8bits, 1 - 16bits, 2 - 32bits, ..., 6 - 512bits)
> > +    allOf:
> > +      - $ref: /schemas/types.yaml#/definitions/uint32
> > +      - enum: [0, 1, 2, 3, 4, 5, 6]
> > +        default: 4
> > +
> > +  snps,priority:
> > +    description: |
> > +      Channel priority specifier associated with the DMA channels.
> > +    allOf:
> > +      - $ref: /schemas/types.yaml#/definitions/uint32-array
> > +      - minItems: 1
> > +        maxItems: 8
> > +        default: [0, 1, 2, 3]
> > +
> > +  snps,block-size:
> > +    description: |
> > +      Channel block size specifier associated with the DMA channels.
> > +    allOf:
> > +      - $ref: /schemas/types.yaml#/definitions/uint32-array
> > +      - minItems: 1
> > +        maxItems: 8
> > +        default: [4096, 4096, 4096, 4096]
> > +
> > +  snps,axi-max-burst-len:
> > +    description: |
> > +      Restrict master AXI burst length by value specified in this prop=
erty.
> > +      If this property is missing the maximum AXI burst length support=
ed by
> > +      DMAC is used. [1:256]
> > +    allOf:
> > +      - $ref: /schemas/types.yaml#/definitions/uint32
> > +        default: 16
> > +
> > +required:
> > +  - compatible
> > +  - reg
> > +  - clocks
> > +  - clock-names
> > +  - interrupts
> > +  - '#dma-cells'
> > +  - dma-channels
> > +  - snps,dma-masters
> > +  - snps,data-width
> > +  - snps,priority
> > +  - snps,block-size
>=20
> Pls add  additionalProperties: false and run latest dt schema tool from R=
ob
[>>] ok. Will add it in v3
>=20
> --
> ~Vinod