Received: by 2002:a05:6a10:16a7:0:0:0:0 with SMTP id gp39csp449058pxb; Wed, 11 Nov 2020 07:39:53 -0800 (PST) X-Google-Smtp-Source: ABdhPJyxZoGLYSf8l/vJmFuiLJ/5p848GaF/3FEG+5p4v3ouwjjjVUCsrPfbwI4rAG+ugyDnhOGj X-Received: by 2002:aa7:da13:: with SMTP id r19mr5834395eds.386.1605109193200; Wed, 11 Nov 2020 07:39:53 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1605109193; cv=none; d=google.com; s=arc-20160816; b=eSK69v62CYprUBqk9/E7JtlNQl8w/s6NJaX5Beh5tDRT/jU40A7wHh2aGY37XJsgf6 sH/6q/bi6QVOLL9FiFrrVKw9p+6iKnxHwhXjc76Q05ihiMaC/YmIRzL6gIkIuZupiwtp bWMTwLhFHIW9BGIKHZWIs/xs7BGrEm2i7G0Wt3PMgwNO30mm0VQFGNWWfHzCzlgcVL5z FZ4fvbPi2sOYmjwOrR0JSmBui/ocJ2VzSfTnhgW1/JkCP4AJXsvkwbtWarCWHdP/4EVN 0sFOG5BP/88lEYaqEhgXVL7EBKxB2qjC2Tyb8oPQIxm1o3xT/WplHZGCZjomKDyq7PDJ tQqA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=nm506Ttw75QB9g3i8XfbJHgDWMXVATaPs9Pwq9jcU6c=; b=iQ77KvQbZnM//+JDNQumJ7xSHF5cgtt+aXYNPkrGQQReg4dxHW/L4uDqJj4+jNnxEI MK2O900nDS0qCWDFLVnoa7B/BcTolWYJCg1G7f6upV268uLxPgjbQezGyuItCrA1w46U r+a/TExRPgD9hfpl4Iwn0hOrSoDFMLlqEqt2it1gsTpdgiiKwCPrUl5lZge4EtH8fx3i VKcYwaWEwJ7a9LwiZN2U00UGUZ5datbuVSBvuxXh2PDdv8ToRKUb8LmJC6cSxxXRmv6B s1oy/VAo8NRK5N3n+D/lte7bfDtYLjCARVnszlcZsklUXWyenOJ6blU7OdRnh364N94F Q/qA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=mNdZm4pW; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id k20si1813409eds.233.2020.11.11.07.39.29; Wed, 11 Nov 2020 07:39:53 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=mNdZm4pW; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727519AbgKKPh3 (ORCPT + 99 others); Wed, 11 Nov 2020 10:37:29 -0500 Received: from fllv0016.ext.ti.com ([198.47.19.142]:38102 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727514AbgKKPh2 (ORCPT ); Wed, 11 Nov 2020 10:37:28 -0500 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 0ABFbDP8097719; Wed, 11 Nov 2020 09:37:13 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1605109033; bh=nm506Ttw75QB9g3i8XfbJHgDWMXVATaPs9Pwq9jcU6c=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=mNdZm4pWSsGuqdsRiw0zs5WjR+DtypUjj2wcReu4kY4nrStsHdJ8zlGmqXGEyd2Sw H098/U133dF7Ca3fSiJWWdx3Hy5nuFL/ISkqgNNiGXdG1sjOBwfHIrZueInULNt/Hw fUAwA5goeyRhX6qwxLys3w04Pk4EYzmETP3u7sKM= Received: from DLEE107.ent.ti.com (dlee107.ent.ti.com [157.170.170.37]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 0ABFbCnV113394 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 11 Nov 2020 09:37:12 -0600 Received: from DLEE108.ent.ti.com (157.170.170.38) by DLEE107.ent.ti.com (157.170.170.37) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Wed, 11 Nov 2020 09:37:12 -0600 Received: from lelv0326.itg.ti.com (10.180.67.84) by DLEE108.ent.ti.com (157.170.170.38) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Wed, 11 Nov 2020 09:37:12 -0600 Received: from a0393678-ssd.dal.design.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 0ABFa03x042109; Wed, 11 Nov 2020 09:37:07 -0600 From: Kishon Vijay Abraham I To: Bjorn Helgaas , Jonathan Corbet , Kishon Vijay Abraham I , Lorenzo Pieralisi , Arnd Bergmann , Jon Mason , Dave Jiang , Allen Hubbe , Tom Joseph , Rob Herring CC: Greg Kroah-Hartman , , , , Subject: [PATCH v8 08/18] PCI: endpoint: Add pci_epc_ops to map MSI irq Date: Wed, 11 Nov 2020 21:05:49 +0530 Message-ID: <20201111153559.19050-9-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201111153559.19050-1-kishon@ti.com> References: <20201111153559.19050-1-kishon@ti.com> MIME-Version: 1.0 Content-Type: text/plain X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add pci_epc_ops to map physical address to MSI address and return MSI data. The physical address is an address in the outbound region. This is required to implement doorbell functionality of NTB (non transparent bridge) wherein EPC on either side of the interface (primary and secondary) can directly write to the physical address (in outbound region) of the other interface to ring doorbell using MSI. Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/endpoint/pci-epc-core.c | 41 +++++++++++++++++++++++++++++ include/linux/pci-epc.h | 8 ++++++ 2 files changed, 49 insertions(+) diff --git a/drivers/pci/endpoint/pci-epc-core.c b/drivers/pci/endpoint/pci-epc-core.c index 3693eca5b030..cc8f9eb2b177 100644 --- a/drivers/pci/endpoint/pci-epc-core.c +++ b/drivers/pci/endpoint/pci-epc-core.c @@ -230,6 +230,47 @@ int pci_epc_raise_irq(struct pci_epc *epc, u8 func_no, } EXPORT_SYMBOL_GPL(pci_epc_raise_irq); +/** + * pci_epc_map_msi_irq() - Map physical address to MSI address and return + * MSI data + * @epc: the EPC device which has the MSI capability + * @func_no: the physical endpoint function number in the EPC device + * @phys_addr: the physical address of the outbound region + * @interrupt_num: the MSI interrupt number + * @entry_size: Size of Outbound address region for each interrupt + * @msi_data: the data that should be written in order to raise MSI interrupt + * with interrupt number as 'interrupt num' + * @msi_addr_offset: Offset of MSI address from the aligned outbound address + * to which the MSI address is mapped + * + * Invoke to map physical address to MSI address and return MSI data. The + * physical address should be an address in the outbound region. This is + * required to implement doorbell functionality of NTB wherein EPC on either + * side of the interface (primary and secondary) can directly write to the + * physical address (in outbound region) of the other interface to ring + * doorbell. + */ +int pci_epc_map_msi_irq(struct pci_epc *epc, u8 func_no, phys_addr_t phys_addr, + u8 interrupt_num, u32 entry_size, u32 *msi_data, + u32 *msi_addr_offset) +{ + int ret; + + if (IS_ERR_OR_NULL(epc)) + return -EINVAL; + + if (!epc->ops->map_msi_irq) + return -EINVAL; + + mutex_lock(&epc->lock); + ret = epc->ops->map_msi_irq(epc, func_no, phys_addr, interrupt_num, + entry_size, msi_data, msi_addr_offset); + mutex_unlock(&epc->lock); + + return ret; +} +EXPORT_SYMBOL_GPL(pci_epc_map_msi_irq); + /** * pci_epc_get_msi() - get the number of MSI interrupt numbers allocated * @epc: the EPC device to which MSI interrupts was requested diff --git a/include/linux/pci-epc.h b/include/linux/pci-epc.h index d9cb3944fb87..b82c9b100e97 100644 --- a/include/linux/pci-epc.h +++ b/include/linux/pci-epc.h @@ -55,6 +55,7 @@ pci_epc_interface_string(enum pci_epc_interface_type type) * @get_msix: ops to get the number of MSI-X interrupts allocated by the RC * from the MSI-X capability register * @raise_irq: ops to raise a legacy, MSI or MSI-X interrupt + * @map_msi_irq: ops to map physical address to MSI address and return MSI data * @start: ops to start the PCI link * @stop: ops to stop the PCI link * @owner: the module owner containing the ops @@ -77,6 +78,10 @@ struct pci_epc_ops { int (*get_msix)(struct pci_epc *epc, u8 func_no); int (*raise_irq)(struct pci_epc *epc, u8 func_no, enum pci_epc_irq_type type, u16 interrupt_num); + int (*map_msi_irq)(struct pci_epc *epc, u8 func_no, + phys_addr_t phys_addr, u8 interrupt_num, + u32 entry_size, u32 *msi_data, + u32 *msi_addr_offset); int (*start)(struct pci_epc *epc); void (*stop)(struct pci_epc *epc); const struct pci_epc_features* (*get_features)(struct pci_epc *epc, @@ -216,6 +221,9 @@ int pci_epc_get_msi(struct pci_epc *epc, u8 func_no); int pci_epc_set_msix(struct pci_epc *epc, u8 func_no, u16 interrupts, enum pci_barno, u32 offset); int pci_epc_get_msix(struct pci_epc *epc, u8 func_no); +int pci_epc_map_msi_irq(struct pci_epc *epc, u8 func_no, + phys_addr_t phys_addr, u8 interrupt_num, + u32 entry_size, u32 *msi_data, u32 *msi_addr_offset); int pci_epc_raise_irq(struct pci_epc *epc, u8 func_no, enum pci_epc_irq_type type, u16 interrupt_num); int pci_epc_start(struct pci_epc *epc); -- 2.17.1