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Message-ID: <f2ff951445d83b0bb73e6ea497039beb8bf92d39.camel@infradead.org>
Subject: Re: [EXTERNAL] [tip: x86/apic] x86/io_apic: Cleanup
 trigger/polarity helpers
From:   David Woodhouse <dwmw2@infradead.org>
To:     Tom Lendacky <thomas.lendacky@amd.com>,
        Thomas Gleixner <tglx@linutronix.de>,
        Borislav Petkov <bp@alien8.de>
Cc:     linux-kernel@vger.kernel.org, x86 <x86@kernel.org>,
        Qian Cai <cai@redhat.com>, Joerg Roedel <joro@8bytes.org>,
        Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
Date:   Wed, 11 Nov 2020 21:19:24 +0000
In-Reply-To: <13f8cb3c-713e-c26e-b2ef-4700f9f6ceac@amd.com>
References: <20201024213535.443185-20-dwmw2@infradead.org>
         <160397373817.397.3191135882528008704.tip-bot2@tip-bot2>
         <e2e06979-cbcf-8771-0b48-c46f2d034aa8@amd.com>
         <20201110061046.GA7290@nazgul.tnic>
         <87d00lgu13.fsf@nanos.tec.linutronix.de>
         <9a003c2f-f59a-43ab-bbd5-861b14436d29@amd.com>
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On Wed, 2020-11-11 at 14:30 -0600, Tom Lendacky wrote:
> On 11/11/20 6:32 AM, David Woodhouse wrote:
> > On Wed, 2020-11-11 at 10:36 +0000, David Woodhouse wrote:
> > > On Wed, 2020-11-11 at 10:46 +0100, Thomas Gleixner wrote:
> > > > Looking at it now with brain awake, the XTSUP stuff is pretty much
> > > > the same as DMAR, which I didn't realize yesterday. The affinity
> > > > notifier muck is not needed when we have a write_msg() function whi=
ch
> > > > twiddles the bits into those other locations.
> > >=20
> > > I kind of hate the fact that it's swizzling those bits through invali=
d
> > > MSI messages, so I did it as its own irqdomain using
> > > irq_domain_create_hierarchy() directly instead of
> > > msi_create_irq_domain().
> >=20
> > Please give this a spin:
> >=20
> > https://git.infradead.org/users/dwmw2/linux.git/shortlog/refs/heads/amd=
vi
>=20
> I had trouble cloning your tree for some reason, so just took the top
> three patches and applied them to the tip tree. This all appears to be
> working. I'll let the IOMMU experts take a closer look (adding Suravee).

Thanks. Exercising it by actually triggering faults and observing the
IOMMU interrupt really working would be quite useful =E2=80=94 on hardware =
with
both INTCAPXT and the older MSI delivery.

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