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[23.128.96.18]) by mx.google.com with ESMTP id v21si2879858ejx.104.2020.11.11.21.41.02; Wed, 11 Nov 2020 21:41:25 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@gmail.com header.s=20161025 header.b=hqYpjrD8; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729510AbgKLFit (ORCPT + 99 others); Thu, 12 Nov 2020 00:38:49 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58490 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729296AbgKLFSj (ORCPT ); Thu, 12 Nov 2020 00:18:39 -0500 Received: from mail-ot1-x342.google.com (mail-ot1-x342.google.com [IPv6:2607:f8b0:4864:20::342]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id F4144C0613D1; Wed, 11 Nov 2020 21:18:38 -0800 (PST) Received: by mail-ot1-x342.google.com with SMTP id k3so4431490otp.12; Wed, 11 Nov 2020 21:18:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=WfgY4NBj+0PmzbiLq+b9+ULskd59tjpCJgRhyG5J0k8=; b=hqYpjrD8LkGtcU9kRUoSDHu9D+nk/BoGIjKN/O4ZTOEsso58G3xzPVJwEtiqnqq/iz EutCOAWnRjPC4M3P4mKu1vAmlysKAJJ39gT67ujEtIEFZnYudURzfEEaFFvoby5PYDeg WGwgQ8oX+IFYpLnbesqy5Ia9/WJUAk2Xl9Dxv6an9vZyDdVb2y8os93JKHiy1AKEouPz ZdURh7ongmDTj7ui0P6A3RoB/Z+s3HqGImY6wP6yiACbPwssgtDy4+QGSZtRfSncp5oP HYpY+qBgimQSDzpzvqB38FTtLcdq0cTY6PTDehza5Drh4GFO/c99hgr7Pt7uK18kFWxs EXyg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=WfgY4NBj+0PmzbiLq+b9+ULskd59tjpCJgRhyG5J0k8=; b=sT18voX3wZ+FBKp905p33mJTTeei1M2VDM2g6vKTo1jhjgnk5dcx2VNNfI1man+6uw reDcLhLLj5x1u1K8ZMakVr8aYw9ZWLCpsGO56GLojur3dHCfbfR/L8eEmWtilzDhq3G9 vFQO2Ts4R+xJcaxcKpwnHtsriSzPZ9jDVG2vikWqHK3NmirFFX3L7NYcaX4Tb3SkdM2i ijpju1FxmWTjHxGjz1iV8HBoyC/Xz/6+0PqmwqE7O+j2ZhMXTeEkYHFq0A4Smy8apl0L hYRSsCUFpvJxW/jFy2njT0a9LHHtKzJUds/lFITi79BNMzGC/vngo2M0jlZjWgda892O Md3g== X-Gm-Message-State: AOAM533/gt990nI+7woIygyNDF1y/DDdZ7jbh3WwNgckDX/T5l0WMy6/ Z8deS9iAdZfB3cHt32BAoVKEc+ldREYtQ45t27Q= X-Received: by 2002:a05:6830:18c9:: with SMTP id v9mr21231685ote.74.1605158318274; Wed, 11 Nov 2020 21:18:38 -0800 (PST) MIME-Version: 1.0 References: <20201111163013.29412-1-sergio.paracuellos@gmail.com> In-Reply-To: From: Sergio Paracuellos Date: Thu, 12 Nov 2020 06:18:27 +0100 Message-ID: Subject: Re: [PATCH 0/7] MIPS: ralink: add CPU clock detection and clock gate driver for MT7621 To: Chuanhong Guo Cc: Michael Turquette , Stephen Boyd , Rob Herring , Thomas Bogendoerfer , John Crispin , Greg Kroah-Hartman , Weijie Gao , jiaxun.yang@flygoat.com, "open list:COMMON CLK FRAMEWORK" , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , open list , "open list:MIPS" , "open list:STAGING SUBSYSTEM" Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Chuanhong, On Thu, Nov 12, 2020 at 2:26 AM Chuanhong Guo wrote: [snip] > > I've already said in previous threads that clock assignment in > current linux kernel is not trustworthy. > I've got the clock plan for mt7621 now. (Can't share it, sorry.) > Most of your clock assumptions above are incorrect. Well, that was of course expected, without a real clock plan this driver was only taking into account Oleksij Rempel suggestions to try to make a driver good enough to properly be maintained :). > I've made a clock driver with gate support a few months ago.[0] > but I don't have much time to really finish it. > Maybe you could rework your clock gate driver based on it. > > [0] https://github.com/981213/linux/commit/2eca1f045e4c3db18c941135464c0d7422ad8133 Thanks for the link, I see there are three more clocks there with frequencies of 125, 250 and 270 Mhz. all of them having main xtal as parent. Ok, I will take this real information into account and will send v2 after a bit of more feedback comes. > -- > Regards, > Chuanhong Guo Best regards, Sergio Paracuellos