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[23.128.96.18]) by mx.google.com with ESMTP id co22si3108315edb.469.2020.11.11.21.41.45; Wed, 11 Nov 2020 21:42:08 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@gmail.com header.s=20161025 header.b="cPsUI/o6"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729539AbgKLFi4 (ORCPT + 99 others); Thu, 12 Nov 2020 00:38:56 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59302 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725860AbgKLFX6 (ORCPT ); Thu, 12 Nov 2020 00:23:58 -0500 Received: from mail-ot1-x343.google.com (mail-ot1-x343.google.com [IPv6:2607:f8b0:4864:20::343]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DD19CC0613D4; Wed, 11 Nov 2020 21:23:57 -0800 (PST) Received: by mail-ot1-x343.google.com with SMTP id k3so4440017otp.12; Wed, 11 Nov 2020 21:23:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=NU0FnSXQ52zfzOppTtAfZgow5m+SuejdPqh1x/iQhIo=; b=cPsUI/o6jcDroRRF15FPKRzNWt/KUk/CDMBgqp+Sepr12C45no3YzDny+TA3uTQXDX xjpSwQcnKxfLjTDGOZtFlnmgs9nmDXv1k1yJVI2PgvuOO4W77RLSiaC4++J3Cbap89rU LXozxq7vhFRkQnlZBRtRYQnreuU98uqKspZ6lDsXTzkwTdEMDOkWYlhkkRJSh4n4ZAMt n3yq0Sr8C72i8m4Sx0mPmUEnOTNWWk+lNGCILpy2/IGnyVLkAMqvdUH0svCROz73rBLQ UdFI4Nit/dBaUbNxQXtHhUUGiBIrPBJnuqFF0bTc+ptDt8mZYs1G5rTgoJNHMx6OtBeC CY4A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=NU0FnSXQ52zfzOppTtAfZgow5m+SuejdPqh1x/iQhIo=; b=EklYhzJzQws8NxYzOI4AqBaoWTHBnWkB9xqOEaKWmuJde5IT6pxiyI20AZcISYmZnO lEldhzYiQmTPRHNFlKyALIyOI3U7ApxsHkQeUYKAC5NYDaUf4QUZwd7FYkcv1jN/wGNN 3JPbOAzHyOQ4/RnUJY091hnhu/0TaCG4KIFp2o9Zd+kfUyrnvaQtJAVs+7nntyAO4EeB zcUNsF58Bt8puKfdIwmrdi4XzAE3o5kKg2/lPhYcFO0u8e1iu1+ex7zSbsfaCyWJHbX5 k2Iy52a75d1i3b4xrSmkmnm2Nt228NGEydn8i5zGLhTcTaKUiDIj11mMLAaLIi+tM55c NZKA== X-Gm-Message-State: AOAM530es8uatiTmFefVPwKL+nsb4zodJYKpxu/MCGyD/6luyoPQVbJd c5YmyHnvfWqQLW5S74e88m+q+nfz0J851xW2jdQ= X-Received: by 2002:a9d:4704:: with SMTP id a4mr19589584otf.236.1605158637343; Wed, 11 Nov 2020 21:23:57 -0800 (PST) MIME-Version: 1.0 References: <20201111163013.29412-1-sergio.paracuellos@gmail.com> In-Reply-To: From: Sergio Paracuellos Date: Thu, 12 Nov 2020 06:23:46 +0100 Message-ID: Subject: Re: [PATCH 0/7] MIPS: ralink: add CPU clock detection and clock gate driver for MT7621 To: Chuanhong Guo Cc: Michael Turquette , Stephen Boyd , Rob Herring , Thomas Bogendoerfer , John Crispin , Greg Kroah-Hartman , Weijie Gao , jiaxun.yang@flygoat.com, "open list:COMMON CLK FRAMEWORK" , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , open list , "open list:MIPS" , "open list:STAGING SUBSYSTEM" Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi, On Thu, Nov 12, 2020 at 2:34 AM Chuanhong Guo wrote: > > On Thu, Nov 12, 2020 at 9:26 AM Chuanhong Guo wrote: > > > > I've already said in previous threads that clock assignment in > > current linux kernel is not trustworthy. > > I've got the clock plan for mt7621 now. (Can't share it, sorry.) > > Most of your clock assumptions above are incorrect. > > I've made a clock driver with gate support a few months ago.[0] > > but I don't have much time to really finish it. > > Maybe you could rework your clock gate driver based on it. > > > > [0] https://github.com/981213/linux/commit/2eca1f045e4c3db18c941135464c0d7422ad8133 > > hsdma/eth/pio clocks are still missing in mediatek doc and > I just made them up in the driver. Correct clock frequency for > them aren't really important for them to work though. > And another part I didn't finish is checking clock support for > every drivers mt7621 used. Many drivers don't explicitly > enable the clock and may be problematic when kernel > gates unused clocks. > Well, I think they are not important either. Also, by default gate register has all the gate bits enabled. When a gate driver is added, the kernel by default will try to disable those clocks that haven't been requested. To avoid weird behaviour because of some drivers are not using properly clocks we have the CLK_IGNORED_UNUSED, which as you can see is currently being used in my code. Using that all seems to work as expected as it is now. > -- > Regards, > Chuanhong Guo Best regards, Sergio Paracuellos