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Subject: Re: [PATCH v2 6/7] arm64: dts: ti: k3-j7200-common-proc-board: Enable
 SERDES0
To:     Kishon Vijay Abraham I <kishon@ti.com>,
        Tero Kristo <t-kristo@ti.com>, Nishanth Menon <nm@ti.com>,
        Rob Herring <robh+dt@kernel.org>,
        Roger Quadros <rogerq@ti.com>, Lee Jones <lee.jones@linaro.org>
CC:     <devicetree@vger.kernel.org>, <linux-pci@vger.kernel.org>,
        <linux-kernel@vger.kernel.org>,
        Bjorn Helgaas <bhelgaas@google.com>,
        <linux-arm-kernel@lists.infradead.org>
References: <20201109170409.4498-1-kishon@ti.com>
 <20201109170409.4498-7-kishon@ti.com>
From:   Vignesh Raghavendra <vigneshr@ti.com>
Message-ID: <e7b2b4e7-fb5e-8504-a1b1-70dc10771264@ti.com>
Date:   Thu, 12 Nov 2020 21:28:21 +0530
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On 11/9/20 10:34 PM, Kishon Vijay Abraham I wrote:
> Add sub-nodes to SERDES0 DT node to represent SERDES0 is connected
> to PCIe and QSGMII (multi-link SERDES).
> 
> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
> ---
>  .../dts/ti/k3-j7200-common-proc-board.dts     | 23 +++++++++++++++++++
>  1 file changed, 23 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
> index ef03e7636b66..65a2e5aeb050 100644
> --- a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
> +++ b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
> @@ -8,6 +8,7 @@
>  #include "k3-j7200-som-p0.dtsi"
>  #include <dt-bindings/net/ti-dp83867.h>
>  #include <dt-bindings/mux/ti-serdes.h>
> +#include <dt-bindings/phy/phy.h>
>  
>  / {
>  	chosen {
> @@ -213,3 +214,25 @@
>  	dr_mode = "otg";
>  	maximum-speed = "high-speed";
>  };
> +
> +&serdes_refclk {
> +	clock-frequency = <100000000>;
> +};

Since this is a reference clk from the board, should the entire node be
here instead of in k3-j7200-main.dtsi?

> +
> +&serdes0 {
> +	serdes0_pcie_link: phy@0 {
> +		reg = <0>;
> +		cdns,num-lanes = <2>;
> +		#phy-cells = <0>;
> +		cdns,phy-type = <PHY_TYPE_PCIE>;
> +		resets = <&serdes_wiz0 1>, <&serdes_wiz0 2>;
> +	};
> +
> +	serdes0_qsgmii_link: phy@1 {
> +		reg = <2>;
> +		cdns,num-lanes = <1>;
> +		#phy-cells = <0>;
> +		cdns,phy-type = <PHY_TYPE_QSGMII>;
> +		resets = <&serdes_wiz0 3>;
> +	};
> +};
>