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From:   =?UTF-8?q?Jonathan=20Neusch=C3=A4fer?= <j.neuschaefer@gmx.net>
To:     linux-input@vger.kernel.org
Cc:     Dmitry Torokhov <dmitry.torokhov@gmail.com>,
        Rob Herring <robh+dt@kernel.org>,
        Shawn Guo <shawnguo@kernel.org>,
        Sascha Hauer <s.hauer@pengutronix.de>,
        Pengutronix Kernel Team <kernel@pengutronix.de>,
        Fabio Estevam <festevam@gmail.com>,
        NXP Linux Team <linux-imx@nxp.com>,
        =?UTF-8?q?Jonathan=20Neusch=C3=A4fer?= <j.neuschaefer@gmx.net>,
        devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
        linux-arm-kernel@lists.infradead.org
Subject: [PATCH v2] ARM: dts: imx50-kobo-aura: Enable eKTF2132 touchscreen
Date:   Fri, 13 Nov 2020 00:30:54 +0100
Message-Id: <20201112233054.3837465-1-j.neuschaefer@gmx.net>
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Precedence: bulk

The Kobo Aura has an eKTF2132 touchscreen controller.

Although the vendor kernel toggles a reset pin (GPIO5-12) during the
startup sequence, the touchscreen works without it.

Signed-off-by: Jonathan Neusch=C3=A4fer <j.neuschaefer@gmx.net>
=2D--

v2:
- Fix devicetree build by adding #include <dt-bindings/interrupt-controlle=
r/irq.h>
- Drop the first two patches, which been applied in the meantime

v1:
- https://lore.kernel.org/lkml/20201106112412.390724-4-j.neuschaefer@gmx.n=
et/
=2D--
 arch/arm/boot/dts/imx50-kobo-aura.dts | 17 ++++++++++++++++-
 1 file changed, 16 insertions(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/imx50-kobo-aura.dts b/arch/arm/boot/dts/imx=
50-kobo-aura.dts
index 53b3995d37e7f..97cfd970fe742 100644
=2D-- a/arch/arm/boot/dts/imx50-kobo-aura.dts
+++ b/arch/arm/boot/dts/imx50-kobo-aura.dts
@@ -6,6 +6,7 @@
 /dts-v1/;
 #include "imx50.dtsi"
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/interrupt-controller/irq.h>

 / {
 	model =3D "Kobo Aura (N514)";
@@ -119,7 +120,14 @@ &i2c1 {
 	pinctrl-0 =3D <&pinctrl_i2c1>;
 	status =3D "okay";

-	/* TODO: ektf2132 touch controller at 0x15 */
+	touchscreen@15 {
+		reg =3D <0x15>;
+		compatible =3D "elan,ektf2132";
+		pinctrl-names =3D "default";
+		pinctrl-0 =3D <&pinctrl_ts>;
+		power-gpios =3D <&gpio4 9 GPIO_ACTIVE_HIGH>;
+		interrupts-extended =3D <&gpio5 13 IRQ_TYPE_EDGE_FALLING>;
+	};
 };

 &i2c2 {
@@ -225,6 +233,13 @@ MX50_PAD_SD3_D7__ESDHC3_DAT7		0x1d4
 		>;
 	};

+	pinctrl_ts: tsgrp {
+		fsl,pins =3D <
+			MX50_PAD_CSPI_MOSI__GPIO4_9		0x0
+			MX50_PAD_SD2_D5__GPIO5_13		0x0
+		>;
+	};
+
 	pinctrl_uart2: uart2grp {
 		fsl,pins =3D <
 			MX50_PAD_UART2_TXD__UART2_TXD_MUX	0x1e4
=2D-
2.28.0