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[23.128.96.18]) by mx.google.com with ESMTP id p22si7037299edy.347.2020.11.13.11.41.09; Fri, 13 Nov 2020 11:41:34 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@nvidia.com header.s=n1 header.b="eJHaj6k/"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=nvidia.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726295AbgKMTg5 (ORCPT + 99 others); Fri, 13 Nov 2020 14:36:57 -0500 Received: from hqnvemgate25.nvidia.com ([216.228.121.64]:15762 "EHLO hqnvemgate25.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726028AbgKMTgz (ORCPT ); Fri, 13 Nov 2020 14:36:55 -0500 Received: from hqmail.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate25.nvidia.com (using TLS: TLSv1.2, AES256-SHA) id ; Fri, 13 Nov 2020 11:36:48 -0800 Received: from HQMAIL105.nvidia.com (172.20.187.12) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Fri, 13 Nov 2020 19:36:54 +0000 Received: from skomatineni-linux.nvidia.com (10.124.1.5) by mail.nvidia.com (172.20.187.12) with Microsoft SMTP Server id 15.0.1473.3 via Frontend Transport; Fri, 13 Nov 2020 19:36:54 +0000 From: Sowjanya Komatineni To: , , , CC: , , , Subject: [PATCH v2 1/6] arm: tegra: Change order of SATA resets for Tegra124 Date: Fri, 13 Nov 2020 11:36:53 -0800 Message-ID: <1605296218-2510-2-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1605296218-2510-1-git-send-email-skomatineni@nvidia.com> References: <1605296218-2510-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Content-Type: text/plain DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1605296208; bh=OVzKks19l7hQ8uUDd0AEy7B6IREE9ECotN1tw04H1tA=; h=From:To:CC:Subject:Date:Message-ID:X-Mailer:In-Reply-To: References:X-NVConfidentiality:MIME-Version:Content-Type; b=eJHaj6k/k+/3oq9lHfvddVW701ia2GyaNb7M2kR3Xclgm61tnGT41q1isOavlMBPf GdP+qFlMWxf/swkBO07P4N0IgX25iGxXecZvfMZcFR7Z7iC4LsKpZf3bOSzkEBP3Uw JkrFJbzUZsrnP13hIvDIIpGirk0ezC9TvWWRzjuV6elDx6bC4dpRTLY3J1mA/rvqD7 B0s2LkWTCJYZWTPnfxyLl+6N3ZzyYrzyhpej8Arf+cizNgCvO+5XnD8TVBhoXc1ANm oUgeHkSxNtaAsbRweGA0h58jX8KSzaeHlJ+ONCncW3AR9ajRd37SrwW+lTMF6cChI2 caVqRaP0WcsBA== Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Tegra AHCI dt-binding doc is converted from text based to yaml based. dtbs_check valdiation strictly follows reset-names order specified in yaml dt-binding. Tegra124 thru Tegra210 has 3 resets sata, sata-oob and sata-cold. Tegra186 has 2 resets sata and sata-cold. This patch changes order of SATA resets to maintain proper resets order for commonly available resets across Tegra124 thru Tegra186 for dtbs_check to pass. Signed-off-by: Sowjanya Komatineni --- arch/arm/boot/dts/tegra124.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi index 64f488b..2e5c840 100644 --- a/arch/arm/boot/dts/tegra124.dtsi +++ b/arch/arm/boot/dts/tegra124.dtsi @@ -650,9 +650,9 @@ <&tegra_car TEGRA124_CLK_PLL_E>; clock-names = "sata", "sata-oob", "cml1", "pll_e"; resets = <&tegra_car 124>, - <&tegra_car 123>, - <&tegra_car 129>; - reset-names = "sata", "sata-oob", "sata-cold"; + <&tegra_car 129>, + <&tegra_car 123>; + reset-names = "sata", "sata-cold", "sata-oob"; status = "disabled"; }; -- 2.7.4