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From:   Geert Uytterhoeven <geert@linux-m68k.org>
Date:   Mon, 16 Nov 2020 10:01:52 +0100
Message-ID: <CAMuHMdXkPDepLkJnGdMO2anzcRm7ofJ5RnWkYtaZM4ZeMOUf9Q@mail.gmail.com>
Subject: Re: [PATCH v3] clk: renesas: r8a774c0: Add RPC clocks
To:     "Lad, Prabhakar" <prabhakar.csengg@gmail.com>
Cc:     Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>,
        Michael Turquette <mturquette@baylibre.com>,
        Stephen Boyd <sboyd@kernel.org>,
        Linux-Renesas <linux-renesas-soc@vger.kernel.org>,
        linux-clk <linux-clk@vger.kernel.org>,
        Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
        Biju Das <biju.das.jz@bp.renesas.com>
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Hi Prabhakar,

On Mon, Nov 16, 2020 at 9:54 AM Lad, Prabhakar
<prabhakar.csengg@gmail.com> wrote:
> On Mon, Nov 16, 2020 at 8:34 AM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
> > On Tue, Nov 10, 2020 at 1:56 PM Lad Prabhakar
> > <prabhakar.mahadev-lad.rj@bp.renesas.com> wrote:
> > > Describe the RPCSRC internal clock and the RPC[D2] clocks derived from it,
> > > as well as the RPC-IF module clock, in the RZ/G2E (R8A774C0) CPG/MSSR
> > > driver.
> > >
> > > Add new clk type CLK_TYPE_GEN3E3_RPCSRC to register rpcsrc as a fixed
> > > clock on R-Car Gen3 E3 (and also RZ/G2E which is identical to E3 SoC),
> > > parent and the divider is set based on the register value CPG_RPCCKCR[4:3]
> > > (parent is cross verified against MD[4:1] pins) which has been set prior
> > > to booting the kernel.
> > >
> > > MD[4] MD[3] MD[2] MD[1]
> > >   0     0     0    1     -> RPCSRC CLK source is PLL1
> > >   0     0     1    1     -> RPCSRC CLK source is PLL1
> > >   0     1     0    0     -> RPCSRC CLK source is PLL1
> > >   1     0     1    1     -> RPCSRC CLK source is PLL1
> > >   x     x     x    x     -> For any other values RPCSRC CLK source is PLL0
> > >
> > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>

> > > +               switch (value) {
> > > +               case 0:
> > > +                       div = 5;
> > > +                       break;
> > > +               case 1:
> > > +                       div = 3;
> > > +                       break;
> > > +               case 2:
> > > +                       parent = clks[core->parent >> 16];
> > > +                       if (IS_ERR(parent))
> > > +                               return ERR_CAST(parent);
> > > +                       div = 8;
> >
> > R-Car D3 is very similar, but uses div = 5 instead of 8.
> > Perhaps this value can be retrieved from cpg_core_clk.div?
> > Of course, we can do that later, when D3 support is added.
> >
> Agreed, should the below be OK ?
>
> #define DEF_FIXED_RPCSRC_E3(_name, _id, _parent0, _parent1, _div)

Fine, but then I would drop the _E3 suffix ;-)

Alternatively, you can just hide the fixed 8 inside the macro, and add a
seperate macro for D3 later.

Up to you.

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds