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From:   Ikjoon Jang <ikjn@chromium.org>
Date:   Mon, 16 Nov 2020 17:24:28 +0800
Message-ID: <CAATdQgCk6cmD35AQ_pHvotA+Mh8tEiYnHkQVzr5L7ZrpU18z1Q@mail.gmail.com>
Subject: Re: [PATCH v1] spi: spi-mtk-nor: add axi clock control for MT8192 spi-nor
To:     Bayi Cheng <bayi.cheng@mediatek.com>
Cc:     Mark Brown <broonie@kernel.org>,
        Matthias Brugger <matthias.bgg@gmail.com>,
        linux-spi@vger.kernel.org,
        "moderated list:ARM/Mediatek SoC support" 
        <linux-arm-kernel@lists.infradead.org>,
        "moderated list:ARM/Mediatek SoC support" 
        <linux-mediatek@lists.infradead.org>,
        open list <linux-kernel@vger.kernel.org>,
        Chuanhong Guo <gch981213@gmail.com>,
        srv_heupstream@mediatek.com
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On Wed, Nov 11, 2020 at 4:55 PM Bayi Cheng <bayi.cheng@mediatek.com> wrote:
>
> From: bayi cheng <bayi.cheng@mediatek.com>
>
> MT8192 spi-nor is an independent sub system, we need extra control axi
> bus clock for it. Add support for the additional axi clock to allow it
> to be configured appropriately.
>
> Signed-off-by: bayi cheng <bayi.cheng@mediatek.com>

Tested-by: Ikjoon Jang <ikjn@chromium.org>

> ---
>  drivers/spi/spi-mtk-nor.c | 16 +++++++++++++++-
>  1 file changed, 15 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/spi/spi-mtk-nor.c b/drivers/spi/spi-mtk-nor.c
> index b97f26a..bf2d0f9 100644
> --- a/drivers/spi/spi-mtk-nor.c
> +++ b/drivers/spi/spi-mtk-nor.c
> @@ -103,6 +103,7 @@ struct mtk_nor {
>         dma_addr_t buffer_dma;
>         struct clk *spi_clk;
>         struct clk *ctlr_clk;
> +       struct clk *axi_clk;
>         unsigned int spi_freq;
>         bool wbuf_en;
>         bool has_irq;
> @@ -672,6 +673,7 @@ static void mtk_nor_disable_clk(struct mtk_nor *sp)
>  {
>         clk_disable_unprepare(sp->spi_clk);
>         clk_disable_unprepare(sp->ctlr_clk);
> +       clk_disable_unprepare(sp->axi_clk);
>  }
>
>  static int mtk_nor_enable_clk(struct mtk_nor *sp)
> @@ -688,6 +690,13 @@ static int mtk_nor_enable_clk(struct mtk_nor *sp)
>                 return ret;
>         }
>
> +       ret = clk_prepare_enable(sp->axi_clk);
> +       if (ret) {
> +               clk_disable_unprepare(sp->spi_clk);
> +               clk_disable_unprepare(sp->ctlr_clk);
> +               return ret;
> +       }
> +
>         return 0;
>  }
>
> @@ -746,7 +755,7 @@ static int mtk_nor_probe(struct platform_device *pdev)
>         struct spi_controller *ctlr;
>         struct mtk_nor *sp;
>         void __iomem *base;
> -       struct clk *spi_clk, *ctlr_clk;
> +       struct clk *spi_clk, *ctlr_clk, *axi_clk;
>         int ret, irq;
>         unsigned long dma_bits;
>
> @@ -762,6 +771,10 @@ static int mtk_nor_probe(struct platform_device *pdev)
>         if (IS_ERR(ctlr_clk))
>                 return PTR_ERR(ctlr_clk);
>
> +       axi_clk = devm_clk_get_optional(&pdev->dev, "axi");
> +       if (IS_ERR(axi_clk))
> +               return PTR_ERR(axi_clk);
> +
>         dma_bits = (unsigned long)of_device_get_match_data(&pdev->dev);
>         if (dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(dma_bits))) {
>                 dev_err(&pdev->dev, "failed to set dma mask(%lu)\n", dma_bits);
> @@ -794,6 +807,7 @@ static int mtk_nor_probe(struct platform_device *pdev)
>         sp->dev = &pdev->dev;
>         sp->spi_clk = spi_clk;
>         sp->ctlr_clk = ctlr_clk;
> +       sp->axi_clk = axi_clk;
>         sp->high_dma = (dma_bits > 32);
>         sp->buffer = dmam_alloc_coherent(&pdev->dev,
>                                 MTK_NOR_BOUNCE_BUF_SIZE + MTK_NOR_DMA_ALIGN,
> --
> 1.9.1
>