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Subject: Re: [PATCHv1 1/4] fpga: fpga-mgr: add
 FPGA_MGR_BITSTREM_AUTHENTICATION flag
To:     Tom Rix <trix@redhat.com>, mdf@kernel.org,
        linux-fpga@vger.kernel.org, linux-kernel@vger.kernel.org
Cc:     dinguyen@kernel.org, sridhar.rajagopal@intel.com,
        Richard Gong <richard.gong@intel.com>
References: <1605204403-6663-1-git-send-email-richard.gong@linux.intel.com>
 <1605204403-6663-2-git-send-email-richard.gong@linux.intel.com>
 <a71b7a9c-effa-ad01-4fde-3e1a1e517e2d@redhat.com>
 <4dd9a747-05f3-1cca-22a6-35681677223d@linux.intel.com>
 <28d2ace8-315a-3eaf-75da-88a4e90ea045@redhat.com>
From:   Richard Gong <richard.gong@linux.intel.com>
Message-ID: <3f8aed65-6010-9220-7635-e8d2726cfc27@linux.intel.com>
Date:   Mon, 16 Nov 2020 07:39:55 -0600
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Hi Tom,

On 11/14/20 9:53 AM, Tom Rix wrote:
> 
> On 11/14/20 6:30 AM, Richard Gong wrote:
>>
>>> A whitespace issue, the new BIT(5) should align with the others, so add two spaces to the others.
>>>
>>
>> There is only one space, also I ran checkpatch with strict option and didn't see any whitespace issue.
>>
>> In the original patch, BIT(0) to BIT(4) align themselves. I am not sure why we see differently in email.
>>
>>   #define FPGA_MGR_PARTIAL_RECONFIG      BIT(0)
>>   #define FPGA_MGR_EXTERNAL_CONFIG       BIT(1)
>>   #define FPGA_MGR_ENCRYPTED_BITSTREAM   BIT(2)
>>   #define FPGA_MGR_BITSTREAM_LSB_FIRST   BIT(3)
>>   #define FPGA_MGR_COMPRESSED_BITSTREAM  BIT(4)
>> +#define FPGA_MGR_BITSTREM_AUTHENTICATION BIT(5)
>>
>> To align BIT(5) with others, I have to use additional tab to BIT(0) to BIT(4). But I don't think I should make such change on them, agree?
> 
> The existing table of #defines has aligned values for BIT(0) to BIT(4)
> 
> Your addition of BIT(5) value has an inconsistent alignment with the others BIT(0) to BIT(4)
> 
> The alignment of all the values should be consistent.
> 

OK, I will make them all aligned.

Regards,
Richard

> Tom
> 
>>
>> Regards,
>> Richard
>>
>>> Tom
>>>
>>>>      /**
>>>>     * struct fpga_image_info - information specific to a FPGA image
>>>
>>
>