Received: by 2002:a05:6a10:16a7:0:0:0:0 with SMTP id gp39csp3132921pxb; Mon, 16 Nov 2020 06:40:57 -0800 (PST) X-Google-Smtp-Source: ABdhPJx2/rhXizFbw0w/Uz+wbkC+c8i+jO/hrzktfkHB6eXTvLV09t0yosbEE9NUdFCBojIZPFGT X-Received: by 2002:aa7:cdd9:: with SMTP id h25mr16213889edw.294.1605537657398; Mon, 16 Nov 2020 06:40:57 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1605537657; cv=none; d=google.com; s=arc-20160816; b=I+zs9cWWOqwWN3XDK6S4nG3MhtzCgPT8zkc7fJb7I4GoHLzKw9wAIrxoeIVNFjYzPl euSEtsvJbb8xq55OwUXA9hdPO649OhfSI+rpq6I3KSM8PqjEAo9jZzrS9z+9Ay0JJWiM GEARf2nL4sK7ZSdSZy2ckibM+UelTf0nVh3QAJXudOvtXW1xHadYv+jB33/6Y+MhcGSJ Rrl0x/EZzZPlm5UAe23Tyd2xXqOWCEFYrOjw4dHnzGanek3s6gVMizPppVw1oy6PSbxV 4FrKW4gfgcby86UhzcbUzyt9NNCbeYw9QQmTa2MzbOHBuCZ/lRlhisJNP/6PGFl/4Bwq cCKw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:in-reply-to:content-disposition:mime-version :references:message-id:subject:cc:to:from:date; bh=AttLbc38mETlXkjn0gWnyNZ5cdX5kRZLWtEe0NPP8tc=; b=ZkFEBvZb+SyY+Adg1b50MZ6HFaoefXiey7GoZC2CYgMbI8cnMolecZmInLjp9SS/4g KxNNpYDqci5oQXVgGxtrz0WZ+G7PeDCE63laQ9CRKJvahOaoQjGdjkpy6GZ+h0nMDZpH lCO9CA6TqO1A4BrqlqiO87/cngRHShRVHWcomBER/9BE+0puFBuVbrEmJsY0ruSyQoGD GD5NAilXKs3JSbtxa5GjbuSvqmS2c9kJOue0H+LHgNYoVBoJT0amEAUJ4qwWo3J72zoF pJFHmndKzh78whr704j/q2Ny/DFq7dil6awVnYXzNcLcIMiBf+OI6xYKw1g3o6T5nxy8 OoLw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id h8si12287349edk.97.2020.11.16.06.40.33; Mon, 16 Nov 2020 06:40:57 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730090AbgKPOil (ORCPT + 99 others); Mon, 16 Nov 2020 09:38:41 -0500 Received: from vps0.lunn.ch ([185.16.172.187]:57504 "EHLO vps0.lunn.ch" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727820AbgKPOil (ORCPT ); Mon, 16 Nov 2020 09:38:41 -0500 Received: from andrew by vps0.lunn.ch with local (Exim 4.94) (envelope-from ) id 1kefeI-007MMi-6h; Mon, 16 Nov 2020 15:38:30 +0100 Date: Mon, 16 Nov 2020 15:38:30 +0100 From: Andrew Lunn To: Martin Blumenstingl Cc: hauke@hauke-m.de, netdev@vger.kernel.org, vivien.didelot@gmail.com, f.fainelli@gmail.com, olteanv@gmail.com, davem@davemloft.net, kuba@kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v2] net: lantiq: Wait for the GPHY firmware to be ready Message-ID: <20201116143830.GD1716542@lunn.ch> References: <20201115165757.552641-1-martin.blumenstingl@googlemail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20201115165757.552641-1-martin.blumenstingl@googlemail.com> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Sun, Nov 15, 2020 at 05:57:57PM +0100, Martin Blumenstingl wrote: > A user reports (slightly shortened from the original message): > libphy: lantiq,xrx200-mdio: probed > mdio_bus 1e108000.switch-mii: MDIO device at address 17 is missing. > gswip 1e108000.switch lan: no phy at 2 > gswip 1e108000.switch lan: failed to connect to port 2: -19 > lantiq,xrx200-net 1e10b308.eth eth0: error -19 setting up slave phy > > This is a single-port board using the internal Fast Ethernet PHY. The > user reports that switching to PHY scanning instead of configuring the > PHY within device-tree works around this issue. > > The documentation for the standalone variant of the PHY11G (which is > probably very similar to what is used inside the xRX200 SoCs but having > the firmware burnt onto that standalone chip in the factory) states that > the PHY needs 300ms to be ready for MDIO communication after releasing > the reset. > > Add a 300ms delay after initializing all GPHYs to ensure that the GPHY > firmware had enough time to initialize and to appear on the MDIO bus. > Unfortunately there is no (known) documentation on what the minimum time > to wait after releasing the reset on an internal PHY so play safe and > take the one for the external variant. Only wait after the last GPHY > firmware is loaded to not slow down the initialization too much ( > xRX200 has two GPHYs but newer SoCs have at least three GPHYs). > > Fixes: 14fceff4771e51 ("net: dsa: Add Lantiq / Intel DSA driver for vrx200") > Reviewed-by: Andrew Lunn > Signed-off-by: Martin Blumenstingl Reviewed-by: Andrew Lunn Andrew