Received: by 2002:a05:6a10:16a7:0:0:0:0 with SMTP id gp39csp3241861pxb; Mon, 16 Nov 2020 09:16:21 -0800 (PST) X-Google-Smtp-Source: ABdhPJx1kfpHuFsIPPbqD5iyzSe7ACmr9n5IcdmO91RjseEbOOYCpT182scrVp5fOi8fXjyJSXWi X-Received: by 2002:aa7:d6c2:: with SMTP id x2mr16053762edr.206.1605546980737; Mon, 16 Nov 2020 09:16:20 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1605546980; cv=none; d=google.com; s=arc-20160816; b=qjsBMxasIwC8rrGMW8oSuIQeYo7t9ePvPs/mThWF1yq6t1nnGdHiBIjj8W8V65jb4y YzANKQPHlVysXzgjPtTUA8Q/KMbjOyQRRae/yQM4ZlAOVVUdJilY/PomL4dOk1VJ5ht1 IAdywyF3ieT752vhnSA25vqKyS8uomf2f1+VDMUNMX+Vg4VVv4GxE+Y6KWXoqNOjAAGs oSieAzULb7bzcX3kDXa/xyPfOVWXsdI6wFQ14hj8UGayMupvQkqOytcBoq8/voMeF+qf CBcEsaTyV6QdbccNqtHdqJqSGZsSUhF7jMaEsjmciiNkWr7i26CpNBdLBBv2q2OGiFs0 94JA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=eZFpuBvKCKQr/VC9jznjIIReCOrqsX+JVQzf2d/cGz0=; b=L5jlVjRyw+bAKijs/VXJX8lI5zQ0icJRWuV4JnZhBFgRYPwJauHwIlmuYvFK1SuOFc OAyU/KLJq9JtLgD3k8AsSNzXc9zOn5XA48QuUAtnl8+gFecp2n8KXUUe1ECPTeFkD8y7 ZxjJwCqy6K3qdb0Ram9VKMQHJusRsyIuaJNL85uOZJsdWk9OynENeMYN40GI8M0F0neh 2CS17ZF8l117oVqpnX6ZEFGhf75LsauCPFi8Bzsl6CTEAF0vc8Mswevp9N5FZ3Ve/eI+ wl4fF0jMvY60pH+0Yz1+6ACyYtKQV1MJDRqluDEFgDMkO33IcP1O+6jQnnk+AlfhYCbt xKpQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id ay1si12019649edb.326.2020.11.16.09.15.56; Mon, 16 Nov 2020 09:16:20 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1732627AbgKPRMT (ORCPT + 99 others); Mon, 16 Nov 2020 12:12:19 -0500 Received: from relay11.mail.gandi.net ([217.70.178.231]:52821 "EHLO relay11.mail.gandi.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731130AbgKPRMT (ORCPT ); Mon, 16 Nov 2020 12:12:19 -0500 X-Greylist: delayed 2863 seconds by postgrey-1.27 at vger.kernel.org; Mon, 16 Nov 2020 12:12:18 EST Received: from localhost (91-175-115-186.subs.proxad.net [91.175.115.186]) (Authenticated sender: gregory.clement@bootlin.com) by relay11.mail.gandi.net (Postfix) with ESMTPSA id 96CFF100041; Mon, 16 Nov 2020 17:12:15 +0000 (UTC) From: Gregory CLEMENT To: Sebastian Reichel , linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Herring , devicetree@vger.kernel.org Cc: Thomas Petazzoni , Alexandre Belloni , Lars Povlsen , Subject: [PATCH 1/5] dt-bindings: reset: ocelot: Add documentation for 'microchip,reset-switch-core' property Date: Mon, 16 Nov 2020 18:11:55 +0100 Message-Id: <20201116171159.1735315-2-gregory.clement@bootlin.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20201116171159.1735315-1-gregory.clement@bootlin.com> References: <20201116171159.1735315-1-gregory.clement@bootlin.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Lars Povlsen This documents the 'microchip,reset-switch-core' property in the ocelot-reset driver. Signed-off-by: Lars Povlsen --- .../devicetree/bindings/power/reset/ocelot-reset.txt | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/power/reset/ocelot-reset.txt b/Documentation/devicetree/bindings/power/reset/ocelot-reset.txt index 4d530d815484..20fff03753ad 100644 --- a/Documentation/devicetree/bindings/power/reset/ocelot-reset.txt +++ b/Documentation/devicetree/bindings/power/reset/ocelot-reset.txt @@ -9,9 +9,15 @@ microchip Sparx5 armv8 SoC's. Required Properties: - compatible: "mscc,ocelot-chip-reset" or "microchip,sparx5-chip-reset" +Optional properties: +- microchip,reset-switch-core : Perform a switch core reset at the + time of driver load. This is may be used to initialize the switch + core to a known state (before other drivers are loaded). + Example: reset@1070008 { compatible = "mscc,ocelot-chip-reset"; reg = <0x1070008 0x4>; + microchip,reset-switch-core; }; -- 2.29.2