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From:   matthew.gerlach@linux.intel.com
To:     linux-fpga@vger.kernel.org, linux-kernel@vger.kernel.org,
        mdf@kernel.org, hao.wu@intel.com, trix@redhat.com,
        linux-doc@vger.kernel.org, corbet@lwn.net
Cc:     Matthew Gerlach <matthew.gerlach@linux.intel.com>
Subject: [PATCH 0/2] fpga: dfl: optional VSEC for start of dfl
Date:   Mon, 16 Nov 2020 17:25:50 -0800
Message-Id: <20201117012552.262149-1-matthew.gerlach@linux.intel.com>
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From: Matthew Gerlach <matthew.gerlach@linux.intel.com>

The start of a Device Feature List (DFL) is currently assumed to be at
Bar0/Offset 0 on the PCIe bus by drivers/fpga/dfl-pci.c.  This patchset
adds support for the start of one or more DFLs to be specified in a
Vendor-Specific Capability (VSEC) structure in PCIe config space.  If no
such VSEC structure exists, then the start of the DFL is assumed to be 
Bar0/Offset 0 for backward compatibility.

Matthew Gerlach (2):
  fpga: dfl: refactor cci_enumerate_feature_devs()
  fpga: dfl: look for vendor specific capability

 Documentation/fpga/dfl.rst |  10 +++
 drivers/fpga/dfl-pci.c     | 168 +++++++++++++++++++++++++++++--------
 2 files changed, 143 insertions(+), 35 deletions(-)

-- 
2.25.2