From: Andi Kleen <ak@suse.de>
To: eranian@hpl.hp.com
Subject: Re: [PATCH 18/18] 2.6.17.9 perfmon2 patch for review: new x86_64 files
Date: Wed, 23 Aug 2006 13:22:44 +0200
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> I have a second thought on this. AMD has architected the performance counters.

Quote:
>>
Implementations are not required to support the performance
c o u n t e rs and the event-select registers, or the time-stamp
counter. The presence of these features can be determined by
<<

Also all code I've seen checked the family at least.


> Their specification is not part of a model specific documentation but
> part of the AMD64 architecure. 

The high level specification is, but not the actual counters for once.

> What I don't not quite understand with the K7, K8 terminology is the
> relation/dependencies with the AMD64 architecture specification.
AMD64 gives a high level register format, K7/K8 is the actual list 
of performance counters.

-Andi

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