From: Andi Kleen <ak@suse.de>
To: eranian@hpl.hp.com
Subject: Re: [PATCH 18/18] 2.6.17.9 perfmon2 patch for review: new x86_64 files
Date: Wed, 23 Aug 2006 14:29:04 +0200
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On Wednesday 23 August 2006 14:14, Stephane Eranian wrote:

[adding discuss@x86-64.org so that possibly AMD people can comment]

> On Wed, Aug 23, 2006 at 01:22:44PM +0200, Andi Kleen wrote:
> > 
> > > I have a second thought on this. AMD has architected the performance counters.
> > 
> > Quote:
> > >>
> > Implementations are not required to support the performance
> > c o u n t e rs and the event-select registers, or the time-stamp
> > counter. The presence of these features can be determined by
> > <<
> > 
> At the end of this paragraph then mention using CPUID to determine
> the presence of the counters. AFAIK, there is no feature bit
> covering performance monitoring. Does that mean we are left
> with having to check the family and model number just like on
> Intel?

Yes I puzzled over that too. Maybe they meant the MSR CPUID bits, but most likely
it was a mistake by the tech writer.

Yes I think you have to. Only checking vendor/family should be fine though -- i am not
aware of performance counter variations between models.

Perhaps add a force argument again that disables the family check too.

> Ok, I think I understand now:
> 	1/ Bios and Kernel Developer Guide from Ahtlon64 and Opteron 64 is
> 	  what you are talking about with K7/K8

Well K8.

K7 has a different one. But ok. I think you don't try to support K7 at all
currently (it has the same register format as K8, but the list of counters
is different)

> 	2/ AMD64 Architecture Programmer's Manual is the generic AMD64 description

Yep
 
-Andi
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