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Tue, 17 Nov 2020 17:09:53 +0000 From: Tom Lendacky To: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, x86@kernel.org Cc: Paolo Bonzini , Jim Mattson , Joerg Roedel , Sean Christopherson , Vitaly Kuznetsov , Wanpeng Li , Borislav Petkov , Ingo Molnar , Thomas Gleixner , Brijesh Singh Subject: [PATCH v4 16/34] KVM: SVM: Add support for SEV-ES GHCB MSR protocol function 0x100 Date: Tue, 17 Nov 2020 11:07:19 -0600 Message-Id: <73021b2cae2341c6cdefdf268f39611e476af0a3.1605632857.git.thomas.lendacky@amd.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: References: Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit X-Originating-IP: [165.204.77.1] X-ClientProxiedBy: DM5PR05CA0002.namprd05.prod.outlook.com (2603:10b6:3:d4::12) To DM5PR12MB1355.namprd12.prod.outlook.com (2603:10b6:3:6e::7) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from tlendack-t1.amd.com (165.204.77.1) by DM5PR05CA0002.namprd05.prod.outlook.com (2603:10b6:3:d4::12) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3589.15 via Frontend Transport; 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X-MS-Exchange-AntiSpam-MessageData: RHbCQpjR3JhHAXWAr71ObVgiSYO9C9Hc9W34ddM6zpL43UX2xeWpqcSl5NZ/e2DgL5KGXcSsHvZfnieXf17MRse+a1pXKPApF28WArAvOwVlbjhCIpaZGGZtIyE1ey6cOY5bLIzghTLZWtBen6ITTRdpB/U2qW0nWbAF2yfVA63LHxSX2CpodCishX/MJFhstSRuWwGm2hL63X672x2Zm0WHJNZ7y3V7Uji2dTZFK+TGHigQdC3Bc7mndPnsN3vB6fqUfTn4tZWcUcbWeY7KgYfJFtq0sOtHf83aqC6Up4Lq7MSoxePRXgcBQvDVucL7JOVFQ69r9JFltZ6ZPiIIIHSpcY5sEtt9WQBRxuXJjZoFujMV6P9dNFhoEoBlDOuGN78WDABPbKx9XDWUdwthQHUNzwW0KfW5Nt9MSwEbvkvOixP7467pefCrltLNM2EYyAqxB8z1OgsbJm4skDElobhZ/VAdjwfjTICwBH+ulMlPH5+4HTZ2F2vPATUMgJTocd3jNlgOAi8WL1bSoL/0a3RpyibjbpE7tF1Fu9WtbX17M3C9ZxBVd3Tw1Madhqk0ytt6MyXfhrw5gzf+fKIYoCAbJp0R7kDd8FtBIhwJ+afMnk6d8LI/u3z/fiBv8nRASSiz13+Iq70bPOdrurZuVw== X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: e749b299-42ce-4efc-e50e-08d88b1b9960 X-MS-Exchange-CrossTenant-AuthSource: DM5PR12MB1355.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Nov 2020 17:09:52.8636 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: tWLteyVfP5PfXCtAYJLIKvv5TtC0S55nXbfJlA8sjNL5oxA/zS6Pl8ojZ7H0t2xEvo/wwnTvhO6seJV4tuJ59g== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR12MB1772 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Tom Lendacky The GHCB specification defines a GHCB MSR protocol using the lower 12-bits of the GHCB MSR (in the hypervisor this corresponds to the GHCB GPA field in the VMCB). Function 0x100 is a request for termination of the guest. The guest has encountered some situation for which it has requested to be terminated. The GHCB MSR value contains the reason for the request. Signed-off-by: Tom Lendacky --- arch/x86/kvm/svm/sev.c | 13 +++++++++++++ arch/x86/kvm/svm/svm.h | 6 ++++++ 2 files changed, 19 insertions(+) diff --git a/arch/x86/kvm/svm/sev.c b/arch/x86/kvm/svm/sev.c index 53bf3ff1d9cc..c2cc38e7400b 100644 --- a/arch/x86/kvm/svm/sev.c +++ b/arch/x86/kvm/svm/sev.c @@ -1574,6 +1574,19 @@ static int sev_handle_vmgexit_msr_protocol(struct vcpu_svm *svm) GHCB_MSR_INFO_POS); break; } + case GHCB_MSR_TERM_REQ: { + u64 reason_set, reason_code; + + reason_set = get_ghcb_msr_bits(svm, + GHCB_MSR_TERM_REASON_SET_MASK, + GHCB_MSR_TERM_REASON_SET_POS); + reason_code = get_ghcb_msr_bits(svm, + GHCB_MSR_TERM_REASON_MASK, + GHCB_MSR_TERM_REASON_POS); + pr_info("SEV-ES guest requested termination: %#llx:%#llx\n", + reason_set, reason_code); + fallthrough; + } default: ret = -EINVAL; } diff --git a/arch/x86/kvm/svm/svm.h b/arch/x86/kvm/svm/svm.h index 0df18bdef4ef..7e3f8e3e0722 100644 --- a/arch/x86/kvm/svm/svm.h +++ b/arch/x86/kvm/svm/svm.h @@ -542,6 +542,12 @@ void svm_vcpu_unblocking(struct kvm_vcpu *vcpu); #define GHCB_MSR_CPUID_REG_POS 30 #define GHCB_MSR_CPUID_REG_MASK 0x3 +#define GHCB_MSR_TERM_REQ 0x100 +#define GHCB_MSR_TERM_REASON_SET_POS 12 +#define GHCB_MSR_TERM_REASON_SET_MASK 0xf +#define GHCB_MSR_TERM_REASON_POS 16 +#define GHCB_MSR_TERM_REASON_MASK 0xff + extern unsigned int max_sev_asid; static inline bool svm_sev_enabled(void) -- 2.28.0