Received: by 2002:a05:6a10:16a7:0:0:0:0 with SMTP id gp39csp4269751pxb; Tue, 17 Nov 2020 16:29:54 -0800 (PST) X-Google-Smtp-Source: ABdhPJzapsvVKuNo0sqnO6iNXwsiDzBllJcNZ94TR+6WBSxYaltE+kGpVWCMbpiVr1Dzb2If75I0 X-Received: by 2002:a50:cd09:: with SMTP id z9mr23963686edi.152.1605659394601; Tue, 17 Nov 2020 16:29:54 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1605659394; cv=none; d=google.com; s=arc-20160816; b=akJPEr6m9kyqk5tXYCyQLhK4T43923c1lzLRz69g2rh30q7oDWXayjPE7jj+O10KHd aa+ilbSmtBoUtYhOsfU8idVVtC4uDsGTjjkXfocf3crGc5Lzyn8LWiskHyDV4okEqrVI GuybjIid0/vcaTFQ+1gm/zqH8vGimc3JRow2fikq8hDdPQiTcs3/CjFnIXFUtkwCLOB4 vxqnfMoUu/yexU5+/kFJHGAk0sCNLP6lLMDoYJkUkKUeSQe+PJ4kE6kBaAn8Rq3dcHJL a+tlJ1GNt9L6Jd8NvTOzg05xl7mcr4oti4VAhM7MLhRBLeBEp0sz/6/Zy0nCIokxa+YZ 0HfQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=nehzPbPtmOws1SJ6lSkadCYi4vtgPlJNFb+bl4QGDmI=; b=m7y9Jj9mwTcA9t+IjEebKOWedOVztPVz5uuvEPKGXFo6UvrW97YUfIp0w7Th7GW/XN BS1n0QL78G40D+G9aqhSTIA3uZzOr/bZNcc4Ji03yrZbNu1fY9x0rCGMjLEI/30zvGu2 7oTRZzc+puDKkCCF8oWcYANzikaO2uuvOTtuHvWbO5eF2rB2t94yYfZkz0+bBhXxjsyF e121k2p00UQsc7XJ9wTz9lEkjU9R9fb5pmNuXv8kNg5i7wu2b6VahrL7hZ7tyPCtchOT 9E1+xuTno2tavg5aqUePxmpQoDsqizONJOB5+mNwQPwrKE7GGKRNGpkoCcHzCnTZk/sI rGFw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id v9si13658548edb.48.2020.11.17.16.29.31; Tue, 17 Nov 2020 16:29:54 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727206AbgKRA1z (ORCPT + 99 others); Tue, 17 Nov 2020 19:27:55 -0500 Received: from relay7-d.mail.gandi.net ([217.70.183.200]:53623 "EHLO relay7-d.mail.gandi.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726977AbgKRA1y (ORCPT ); Tue, 17 Nov 2020 19:27:54 -0500 X-Originating-IP: 86.194.74.19 Received: from localhost (lfbn-lyo-1-997-19.w86-194.abo.wanadoo.fr [86.194.74.19]) (Authenticated sender: alexandre.belloni@bootlin.com) by relay7-d.mail.gandi.net (Postfix) with ESMTPSA id 901D220002; Wed, 18 Nov 2020 00:27:52 +0000 (UTC) From: Alexandre Belloni To: Alessandro Zummo , Alexandre Belloni Cc: linux-rtc@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 3/3] rtc: pcf8523: use BIT Date: Wed, 18 Nov 2020 01:27:47 +0100 Message-Id: <20201118002747.1346504-3-alexandre.belloni@bootlin.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20201118002747.1346504-1-alexandre.belloni@bootlin.com> References: <20201118002747.1346504-1-alexandre.belloni@bootlin.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Use the BIT macro to define register bits. Signed-off-by: Alexandre Belloni --- drivers/rtc/rtc-pcf8523.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/drivers/rtc/rtc-pcf8523.c b/drivers/rtc/rtc-pcf8523.c index d5f913cb2ec9..5e1e7b2a8c9a 100644 --- a/drivers/rtc/rtc-pcf8523.c +++ b/drivers/rtc/rtc-pcf8523.c @@ -12,18 +12,18 @@ #define DRIVER_NAME "rtc-pcf8523" #define REG_CONTROL1 0x00 -#define REG_CONTROL1_CAP_SEL (1 << 7) -#define REG_CONTROL1_STOP (1 << 5) +#define REG_CONTROL1_CAP_SEL BIT(7) +#define REG_CONTROL1_STOP BIT(5) #define REG_CONTROL3 0x02 -#define REG_CONTROL3_PM_BLD (1 << 7) /* battery low detection disabled */ -#define REG_CONTROL3_PM_VDD (1 << 6) /* switch-over disabled */ -#define REG_CONTROL3_PM_DSM (1 << 5) /* direct switching mode */ +#define REG_CONTROL3_PM_BLD BIT(7) /* battery low detection disabled */ +#define REG_CONTROL3_PM_VDD BIT(6) /* switch-over disabled */ +#define REG_CONTROL3_PM_DSM BIT(5) /* direct switching mode */ #define REG_CONTROL3_PM_MASK 0xe0 -#define REG_CONTROL3_BLF (1 << 2) /* battery low bit, read-only */ +#define REG_CONTROL3_BLF BIT(2) /* battery low bit, read-only */ #define REG_SECONDS 0x03 -#define REG_SECONDS_OS (1 << 7) +#define REG_SECONDS_OS BIT(7) #define REG_MINUTES 0x04 #define REG_HOURS 0x05 -- 2.28.0