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From:   Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
To:     jingoohan1@gmail.com, bhelgaas@google.com,
        amurray@thegoodpenguin.co.uk, jonathanh@nvidia.com,
        gustavo.pimentel@synopsys.com, robh@kernel.org,
        Vidya Sagar <vidyas@nvidia.com>, treding@nvidia.com
Cc:     Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
        linux-pci@vger.kernel.org, kthota@nvidia.com,
        linux-kernel@vger.kernel.org, mmaddireddy@nvidia.com,
        sagar.tv@gmail.com
Subject: Re: [PATCH V2 0/2] Add support to handle prefetchable memory
Date:   Wed, 18 Nov 2020 16:18:47 +0000
Message-Id: <160571623360.10954.9426111019711925652.b4-ty@arm.com>
In-Reply-To: <20201118144626.32189-1-vidyas@nvidia.com>
References: <20201118144626.32189-1-vidyas@nvidia.com>
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On Wed, 18 Nov 2020 20:16:24 +0530, Vidya Sagar wrote:
> This patch series adds support for configuring the DesignWare IP's ATU
> region for prefetchable memory translations.
> It first starts by flagging a warning if the size of non-prefetchable
> aperture goes beyond 32-bit as PCIe spec doesn't allow it.
> And then adds required support for programming the ATU to handle higher
> (i.e. >4GB) sizes.
> 
> [...]

Applied to pci/dwc, thanks!

[1/2] PCI: of: Warn if non-prefetchable memory aperture size is > 32-bit
      https://git.kernel.org/lpieralisi/pci/c/fede8526cc
[2/2] PCI: dwc: Add support to program ATU for >4GB memory
      https://git.kernel.org/lpieralisi/pci/c/74081de4a1

Thanks,
Lorenzo