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[104.57.184.186]) by smtp.gmail.com with ESMTPSA id m2sm746892ots.11.2020.11.18.21.45.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Nov 2020 21:45:04 -0800 (PST) Date: Wed, 18 Nov 2020 23:45:03 -0600 From: Bjorn Andersson To: Georgi Djakov Cc: mdtipton@codeaurora.org, linux-pm@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v2] interconnect: qcom: qcs404: Remove GPU and display RPM IDs Message-ID: <20201119054503.GK8532@builder.lan> References: <20201118111044.26056-1-georgi.djakov@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20201118111044.26056-1-georgi.djakov@linaro.org> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed 18 Nov 05:10 CST 2020, Georgi Djakov wrote: > The following errors are noticed during boot on a QCS404 board: > [ 2.926647] qcom_icc_rpm_smd_send mas 6 error -6 > [ 2.934573] qcom_icc_rpm_smd_send mas 8 error -6 > > These errors show when we try to configure the GPU and display nodes. > Since these particular nodes aren't supported on RPM and are purely > local, we should just change their mas_rpm_id to -1 to avoid any > requests being sent for these master IDs. > Reviewed-by: Bjorn Andersson Regards, Bjorn > Signed-off-by: Georgi Djakov > --- > > v2: > * Keep the nodes and just set the IDs to -1, as suggested by Mike. > > v1: http://lore.kernel.org/r/20201111100734.307-1-georgi.djakov@linaro.org > > drivers/interconnect/qcom/qcs404.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/interconnect/qcom/qcs404.c b/drivers/interconnect/qcom/qcs404.c > index d4769a5ea182..9820709b43db 100644 > --- a/drivers/interconnect/qcom/qcs404.c > +++ b/drivers/interconnect/qcom/qcs404.c > @@ -157,8 +157,8 @@ struct qcom_icc_desc { > } > > DEFINE_QNODE(mas_apps_proc, QCS404_MASTER_AMPSS_M0, 8, 0, -1, QCS404_SLAVE_EBI_CH0, QCS404_BIMC_SNOC_SLV); > -DEFINE_QNODE(mas_oxili, QCS404_MASTER_GRAPHICS_3D, 8, 6, -1, QCS404_SLAVE_EBI_CH0, QCS404_BIMC_SNOC_SLV); > -DEFINE_QNODE(mas_mdp, QCS404_MASTER_MDP_PORT0, 8, 8, -1, QCS404_SLAVE_EBI_CH0, QCS404_BIMC_SNOC_SLV); > +DEFINE_QNODE(mas_oxili, QCS404_MASTER_GRAPHICS_3D, 8, -1, -1, QCS404_SLAVE_EBI_CH0, QCS404_BIMC_SNOC_SLV); > +DEFINE_QNODE(mas_mdp, QCS404_MASTER_MDP_PORT0, 8, -1, -1, QCS404_SLAVE_EBI_CH0, QCS404_BIMC_SNOC_SLV); > DEFINE_QNODE(mas_snoc_bimc_1, QCS404_SNOC_BIMC_1_MAS, 8, 76, -1, QCS404_SLAVE_EBI_CH0); > DEFINE_QNODE(mas_tcu_0, QCS404_MASTER_TCU_0, 8, -1, -1, QCS404_SLAVE_EBI_CH0, QCS404_BIMC_SNOC_SLV); > DEFINE_QNODE(mas_spdm, QCS404_MASTER_SPDM, 4, -1, -1, QCS404_PNOC_INT_3);