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Thu, 19 Nov 2020 17:31:00 +0000 Date: Thu, 19 Nov 2020 19:30:55 +0200 From: Laurentiu Palcu To: Liu Ying Cc: linux-arm-kernel@lists.infradead.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, tzimmermann@suse.de, airlied@linux.ie, s.hauer@pengutronix.de, robh+dt@kernel.org, linux-imx@nxp.com, kernel@pengutronix.de, shawnguo@kernel.org Subject: Re: [PATCH 0/8] drm/imx: Introduce i.MX8qxp DPU DRM Message-ID: <20201119173055.geaaori62wgtrfvh@fsr-ub1864-141> References: <1605777745-23625-1-git-send-email-victor.liu@nxp.com> Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1605777745-23625-1-git-send-email-victor.liu@nxp.com> User-Agent: NeoMutt/20171215 X-Originating-IP: [83.217.231.2] X-ClientProxiedBy: AM4PR0302CA0014.eurprd03.prod.outlook.com (2603:10a6:205:2::27) To VI1PR0402MB3902.eurprd04.prod.outlook.com (2603:10a6:803:22::27) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from fsr-ub1864-141 (83.217.231.2) by AM4PR0302CA0014.eurprd03.prod.outlook.com (2603:10a6:205:2::27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3589.20 via Frontend Transport; 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X-MS-Exchange-AntiSpam-MessageData: IlMR5aXYIwZGFO7fDGIaIee9gCqh4YOfWN71TPaPJ+E6Q1fy0xz6ckeKUI0k8pZbO0mI2joScm6aehQKVTgpDK8V3hmpDRgsxiBTwNjRXB3UdnlfmLtOn6wAHymtg6ifltHjUZa9iFK5DeaMvRkK7lmOjCGivD8zEAl5bH+oW16wj1R9gqcx4VjVcNU/3uUdXWEX9jkkXdjS+kc5RSMGbaSva7LVuVsye0CWAZyxu0vMQHNHN2sMLMn7l3qCTo7kkVaJ6Bam+iY+eW6oFhjqGMrDcjBoQz+9UrzeJrNiYUPqljld49zsytjzDSSVUjDoR2elhzEFIioMrFZGjGYCYPuOHaQ0cHSBUi4mMN1FlAWpGBDxOKPQJNHsn+tIx17xGdXwzHNgBV/61cnOdkUPcOu1rWzFviFx4tvAD/gDDDicEu8OvbuZ01gUCmX3JwJR7TIU9bMAnI2anyRkQJsZSNfx5coN3t0bRREqqxkhEAu/8+N6i7ZQ0iFLuHjSSH1SxOuVnsD5nJme1M/4Mtwen7lYzd+EfR7++oH8WZCLoHq+2SmHqVuSkGLNpLD03CH/SpkG3TFzsxZEht7EnCRNiKj3izZFX3JYxlCoKxMwrbmgZqbGEocToXXW5BzMJinVFh9vfO6xjHIwkEQjpAnTdET6K+y+c2c1riFubQ0vT3Y+GyPwuT5LOqdzINq1kUzNfHY9qqgV/Y/BECMMhC28KRfV/0bdz+0bg75qlDjKhI0kXfd1RRmSaJnYYs5Pg69I9EbNRKT3It8NNyLEYlHGjYhUaG2jj/0X6zLj5I5tj0TT7P1oqepbjZ+BUvyIcloR/6wnFuHqadQc8yoINjYMFL1C6sZXE1n3YgVtvt0wNhTF4+RdapW3N9tLKbEoepqX3wzdWr2ISR0LKLnuRd+Nig== X-OriginatorOrg: oss.nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: bb5aa52d-c5ad-40ff-4f9b-08d88cb0e14b X-MS-Exchange-CrossTenant-AuthSource: VI1PR0402MB3902.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Nov 2020 17:30:59.8934 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: +5xhGWxOmN8WOV+2NG1Y+UvU20HGU6fd5nx2GUQQoi9trsU06QWy4lZ2eRiTaES6mG49sWTRpfKDJMB8fLesjA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: VI1PR04MB4477 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Liu Ying, On Thu, Nov 19, 2020 at 05:22:17PM +0800, Liu Ying wrote: > Hi, > > > This patch set introduces i.MX8qxp Display Processing Unit(DPU) DRM support. Glad to see this series out. However, something went wrong with it as patch 5/8 didn't make it to dri-devel mailing list... :/ https://lists.freedesktop.org/archives/dri-devel/2020-November/thread.html So, people on to dri-devel may not be able to review it... However, it did make it to LKML: https://lkml.org/lkml/2020/11/19/249 Not sure what happened here... :/ Thanks, laurentiu > > DPU is comprised of a blit engine for 2D graphics, a display controller > and a command sequencer. Outside of DPU, optional prefetch engines can > fetch data from memory prior to some DPU fetchunits of blit engine and > display controller. The pre-fetchers support linear formats and Vivante > GPU tile formats. > > Reference manual can be found at: > https://www.nxp.com/webapp/Download?colCode=IMX8DQXPRM > > > This patch set adds kernel modesetting support for the display controller part. > It supports two CRTCs per display controller, several planes, prefetch > engines and some properties of CRTC and plane. Currently, the registers of > the controller is accessed without command sequencer involved, instead just by > using CPU. DRM connectors would be created from the DPU KMS driver. > > > If people want to try this series, clock patches can be found at: > https://www.spinics.net/lists/arm-kernel/msg856137.html > > and, power domain patches at: > https://www.spinics.net/lists/arm-kernel/msg856097.html > > > I will send other patch sets to add downstream bridges(embedded in i.MX8qxp) > to support LVDS displays. > > A brief look at the pipe: > prefetch eng -> DPU -> pixel combiner -> pixel link -> pixel to DPI(pxl2dpi) -> > LVDS display bridge(LDB) > > > Patch 1 ~ 3 add dt-bindings for DPU and prefetch engines. > Patch 4 is a minor improvement of a macro to suppress warning as the KMS driver > uses it. > Patch 5 introduces the DPU DRM support. > Patch 6 updates MAINTAINERS. > Patch 7 & 8 add DPU and prefetch engines support in the device tree of > i.MX8qxp MEK platform. > > > Welcome comments, thanks. > > > Liu Ying (8): > dt-bindings: display: imx: Add i.MX8qxp/qm DPU binding > dt-bindings: display: imx: Add i.MX8qxp/qm PRG binding > dt-bindings: display: imx: Add i.MX8qxp/qm DPR channel binding > drm/atomic: Avoid unused-but-set-variable warning on > for_each_old_plane_in_state > drm/imx: Introduce i.MX8qxp DPU DRM > MAINTAINERS: add maintainer for i.MX8qxp DPU DRM driver > arm64: imx8qxp:dtsi: Introduce DC0 subsystem > arm64: dts: imx8qxp-mek: Enable DPU and it's prefetch engines > > .../bindings/display/imx/fsl,imx8qxp-dprc.yaml | 87 ++ > .../bindings/display/imx/fsl,imx8qxp-dpu.yaml | 358 ++++++++ > .../bindings/display/imx/fsl,imx8qxp-prg.yaml | 60 ++ > MAINTAINERS | 9 + > arch/arm64/boot/dts/freescale/imx8qxp-mek.dts | 64 ++ > arch/arm64/boot/dts/freescale/imx8qxp.dtsi | 313 +++++++ > drivers/gpu/drm/imx/Kconfig | 1 + > drivers/gpu/drm/imx/Makefile | 1 + > drivers/gpu/drm/imx/dpu/Kconfig | 10 + > drivers/gpu/drm/imx/dpu/Makefile | 10 + > drivers/gpu/drm/imx/dpu/dpu-constframe.c | 170 ++++ > drivers/gpu/drm/imx/dpu/dpu-core.c | 880 ++++++++++++++++++++ > drivers/gpu/drm/imx/dpu/dpu-crtc.c | 926 +++++++++++++++++++++ > drivers/gpu/drm/imx/dpu/dpu-crtc.h | 62 ++ > drivers/gpu/drm/imx/dpu/dpu-disengcfg.c | 114 +++ > drivers/gpu/drm/imx/dpu/dpu-dprc.c | 721 ++++++++++++++++ > drivers/gpu/drm/imx/dpu/dpu-dprc.h | 40 + > drivers/gpu/drm/imx/dpu/dpu-drv.c | 296 +++++++ > drivers/gpu/drm/imx/dpu/dpu-drv.h | 28 + > drivers/gpu/drm/imx/dpu/dpu-extdst.c | 296 +++++++ > drivers/gpu/drm/imx/dpu/dpu-fetchdecode.c | 291 +++++++ > drivers/gpu/drm/imx/dpu/dpu-fetcheco.c | 221 +++++ > drivers/gpu/drm/imx/dpu/dpu-fetchlayer.c | 151 ++++ > drivers/gpu/drm/imx/dpu/dpu-fetchunit.c | 609 ++++++++++++++ > drivers/gpu/drm/imx/dpu/dpu-fetchunit.h | 191 +++++ > drivers/gpu/drm/imx/dpu/dpu-fetchwarp.c | 247 ++++++ > drivers/gpu/drm/imx/dpu/dpu-framegen.c | 392 +++++++++ > drivers/gpu/drm/imx/dpu/dpu-gammacor.c | 220 +++++ > drivers/gpu/drm/imx/dpu/dpu-hscaler.c | 272 ++++++ > drivers/gpu/drm/imx/dpu/dpu-kms.c | 543 ++++++++++++ > drivers/gpu/drm/imx/dpu/dpu-kms.h | 23 + > drivers/gpu/drm/imx/dpu/dpu-layerblend.c | 345 ++++++++ > drivers/gpu/drm/imx/dpu/dpu-plane.c | 703 ++++++++++++++++ > drivers/gpu/drm/imx/dpu/dpu-plane.h | 56 ++ > drivers/gpu/drm/imx/dpu/dpu-prg.c | 389 +++++++++ > drivers/gpu/drm/imx/dpu/dpu-prg.h | 45 + > drivers/gpu/drm/imx/dpu/dpu-prv.h | 203 +++++ > drivers/gpu/drm/imx/dpu/dpu-tcon.c | 249 ++++++ > drivers/gpu/drm/imx/dpu/dpu-vscaler.c | 305 +++++++ > drivers/gpu/drm/imx/dpu/dpu.h | 389 +++++++++ > include/drm/drm_atomic.h | 4 +- > 41 files changed, 10293 insertions(+), 1 deletion(-) > create mode 100644 Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dprc.yaml > create mode 100644 Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dpu.yaml > create mode 100644 Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-prg.yaml > create mode 100644 drivers/gpu/drm/imx/dpu/Kconfig > create mode 100644 drivers/gpu/drm/imx/dpu/Makefile > create mode 100644 drivers/gpu/drm/imx/dpu/dpu-constframe.c > create mode 100644 drivers/gpu/drm/imx/dpu/dpu-core.c > create mode 100644 drivers/gpu/drm/imx/dpu/dpu-crtc.c > create mode 100644 drivers/gpu/drm/imx/dpu/dpu-crtc.h > create mode 100644 drivers/gpu/drm/imx/dpu/dpu-disengcfg.c > create mode 100644 drivers/gpu/drm/imx/dpu/dpu-dprc.c > create mode 100644 drivers/gpu/drm/imx/dpu/dpu-dprc.h > create mode 100644 drivers/gpu/drm/imx/dpu/dpu-drv.c > create mode 100644 drivers/gpu/drm/imx/dpu/dpu-drv.h > create mode 100644 drivers/gpu/drm/imx/dpu/dpu-extdst.c > create mode 100644 drivers/gpu/drm/imx/dpu/dpu-fetchdecode.c > create mode 100644 drivers/gpu/drm/imx/dpu/dpu-fetcheco.c > create mode 100644 drivers/gpu/drm/imx/dpu/dpu-fetchlayer.c > create mode 100644 drivers/gpu/drm/imx/dpu/dpu-fetchunit.c > create mode 100644 drivers/gpu/drm/imx/dpu/dpu-fetchunit.h > create mode 100644 drivers/gpu/drm/imx/dpu/dpu-fetchwarp.c > create mode 100644 drivers/gpu/drm/imx/dpu/dpu-framegen.c > create mode 100644 drivers/gpu/drm/imx/dpu/dpu-gammacor.c > create mode 100644 drivers/gpu/drm/imx/dpu/dpu-hscaler.c > create mode 100644 drivers/gpu/drm/imx/dpu/dpu-kms.c > create mode 100644 drivers/gpu/drm/imx/dpu/dpu-kms.h > create mode 100644 drivers/gpu/drm/imx/dpu/dpu-layerblend.c > create mode 100644 drivers/gpu/drm/imx/dpu/dpu-plane.c > create mode 100644 drivers/gpu/drm/imx/dpu/dpu-plane.h > create mode 100644 drivers/gpu/drm/imx/dpu/dpu-prg.c > create mode 100644 drivers/gpu/drm/imx/dpu/dpu-prg.h > create mode 100644 drivers/gpu/drm/imx/dpu/dpu-prv.h > create mode 100644 drivers/gpu/drm/imx/dpu/dpu-tcon.c > create mode 100644 drivers/gpu/drm/imx/dpu/dpu-vscaler.c > create mode 100644 drivers/gpu/drm/imx/dpu/dpu.h > > -- > 2.7.4 > > _______________________________________________ > dri-devel mailing list > dri-devel@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/dri-devel