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References: <20201118082126.42701-1-chunfeng.yun@mediatek.com> <20201118082126.42701-6-chunfeng.yun@mediatek.com>
In-Reply-To: <20201118082126.42701-6-chunfeng.yun@mediatek.com>
From:   Chun-Kuang Hu <chunkuang.hu@kernel.org>
Date:   Fri, 20 Nov 2020 07:42:35 +0800
Message-ID: <CAAOTY_9dNyySJkyX78tHDQZPaqD+5Jqixbdbohp319FyXO1X5Q@mail.gmail.com>
Subject: Re: [PATCH v3 06/11] dt-bindings: phy: convert HDMI PHY binding to
 YAML schema
To:     Chunfeng Yun <chunfeng.yun@mediatek.com>
Cc:     Rob Herring <robh+dt@kernel.org>,
        Serge Semin <Sergey.Semin@baikalelectronics.ru>,
        Chun-Kuang Hu <chunkuang.hu@kernel.org>,
        Philipp Zabel <p.zabel@pengutronix.de>,
        David Airlie <airlied@linux.ie>,
        Daniel Vetter <daniel@ffwll.ch>,
        "David S . Miller" <davem@davemloft.net>,
        Jakub Kicinski <kuba@kernel.org>,
        Kishon Vijay Abraham I <kishon@ti.com>,
        Vinod Koul <vkoul@kernel.org>,
        Matthias Brugger <matthias.bgg@gmail.com>,
        Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
        Stanley Chu <stanley.chu@mediatek.com>,
        Min Guo <min.guo@mediatek.com>,
        DRI Development <dri-devel@lists.freedesktop.org>,
        DTML <devicetree@vger.kernel.org>,
        linux-kernel <linux-kernel@vger.kernel.org>,
        netdev@vger.kernel.org,
        Linux ARM <linux-arm-kernel@lists.infradead.org>,
        "moderated list:ARM/Mediatek SoC support" 
        <linux-mediatek@lists.infradead.org>, linux-usb@vger.kernel.org
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Hi, Chunfeng:

Chunfeng Yun <chunfeng.yun@mediatek.com> =E6=96=BC 2020=E5=B9=B411=E6=9C=88=
18=E6=97=A5 =E9=80=B1=E4=B8=89 =E4=B8=8B=E5=8D=884:21=E5=AF=AB=E9=81=93=EF=
=BC=9A
>
> Convert HDMI PHY binding to YAML schema mediatek,hdmi-phy.yaml
>
> Cc: Chun-Kuang Hu <chunkuang.hu@kernel.org>
> Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
> Reviewed-by: Rob Herring <robh@kernel.org>
> ---
> v3: add Reviewed-by Rob
> v2: fix binding check warning of reg in example
> ---
>  .../display/mediatek/mediatek,hdmi.txt        | 18 +---
>  .../bindings/phy/mediatek,hdmi-phy.yaml       | 91 +++++++++++++++++++
>  2 files changed, 92 insertions(+), 17 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/phy/mediatek,hdmi-p=
hy.yaml
>
> diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,=
hdmi.txt b/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi=
.txt
> index 6b1c586403e4..b284ca51b913 100644
> --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.tx=
t
> +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.tx=
t
> @@ -53,23 +53,7 @@ Required properties:
>
>  HDMI PHY
>  =3D=3D=3D=3D=3D=3D=3D=3D
> -
> -The HDMI PHY serializes the HDMI encoder's three channel 10-bit parallel
> -output and drives the HDMI pads.
> -
> -Required properties:
> -- compatible: "mediatek,<chip>-hdmi-phy"
> -- the supported chips are mt2701, mt7623 and mt8173
> -- reg: Physical base address and length of the module's registers
> -- clocks: PLL reference clock
> -- clock-names: must contain "pll_ref"
> -- clock-output-names: must be "hdmitx_dig_cts" on mt8173
> -- #phy-cells: must be <0>
> -- #clock-cells: must be <0>
> -
> -Optional properties:
> -- mediatek,ibias: TX DRV bias current for <1.65Gbps, defaults to 0xa
> -- mediatek,ibias_up: TX DRV bias current for >1.65Gbps, defaults to 0x1c
> +See phy/mediatek,hdmi-phy.yaml
>
>  Example:
>
> diff --git a/Documentation/devicetree/bindings/phy/mediatek,hdmi-phy.yaml=
 b/Documentation/devicetree/bindings/phy/mediatek,hdmi-phy.yaml
> new file mode 100644
> index 000000000000..96700bb8bc00
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/mediatek,hdmi-phy.yaml
> @@ -0,0 +1,91 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +# Copyright (c) 2020 MediaTek
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/phy/mediatek,hdmi-phy.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: MediaTek High Definition Multimedia Interface (HDMI) PHY binding
> +
> +maintainers:
> +  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
> +  - Chunfeng Yun <chunfeng.yun@mediatek.com>

Please add Philipp Zabel because he is Mediatek DRM driver maintainer.

DRM DRIVERS FOR MEDIATEK
M: Chun-Kuang Hu <chunkuang.hu at kernel.org>
M: Philipp Zabel <p.zabel at pengutronix.de>
L: dri-devel at lists.freedesktop.org
S: Supported
F: Documentation/devicetree/bindings/display/mediatek/

Regards,
Chun-Kuang.

> +
> +description: |
> +  The HDMI PHY serializes the HDMI encoder's three channel 10-bit parall=
el
> +  output and drives the HDMI pads.
> +
> +properties:
> +  $nodename:
> +    pattern: "^hdmi-phy@[0-9a-f]+$"
> +
> +  compatible:
> +    enum:
> +      - mediatek,mt2701-hdmi-phy
> +      - mediatek,mt7623-hdmi-phy
> +      - mediatek,mt8173-hdmi-phy
> +
> +  reg:
> +    maxItems: 1
> +
> +  clocks:
> +    items:
> +      - description: PLL reference clock
> +
> +  clock-names:
> +    items:
> +      - const: pll_ref
> +
> +  clock-output-names:
> +    items:
> +      - const: hdmitx_dig_cts
> +
> +  "#phy-cells":
> +    const: 0
> +
> +  "#clock-cells":
> +    const: 0
> +
> +  mediatek,ibias:
> +    description:
> +      TX DRV bias current for < 1.65Gbps
> +    $ref: /schemas/types.yaml#/definitions/uint32
> +    minimum: 0
> +    maximum: 63
> +    default: 0xa
> +
> +  mediatek,ibias_up:
> +    description:
> +      TX DRV bias current for >=3D 1.65Gbps
> +    $ref: /schemas/types.yaml#/definitions/uint32
> +    minimum: 0
> +    maximum: 63
> +    default: 0x1c
> +
> +required:
> +  - compatible
> +  - reg
> +  - clocks
> +  - clock-names
> +  - clock-output-names
> +  - "#phy-cells"
> +  - "#clock-cells"
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +    #include <dt-bindings/clock/mt8173-clk.h>
> +    hdmi_phy: hdmi-phy@10209100 {
> +        compatible =3D "mediatek,mt8173-hdmi-phy";
> +        reg =3D <0x10209100 0x24>;
> +        clocks =3D <&apmixedsys CLK_APMIXED_HDMI_REF>;
> +        clock-names =3D "pll_ref";
> +        clock-output-names =3D "hdmitx_dig_cts";
> +        mediatek,ibias =3D <0xa>;
> +        mediatek,ibias_up =3D <0x1c>;
> +        #clock-cells =3D <0>;
> +        #phy-cells =3D <0>;
> +    };
> +
> +...
> --
> 2.18.0
>