Received: by 2002:a05:6a10:16a7:0:0:0:0 with SMTP id gp39csp1112874pxb; Fri, 20 Nov 2020 01:11:08 -0800 (PST) X-Google-Smtp-Source: ABdhPJxEkUUTLZbcH0spRiezHyIv8wHX/GaD7BScu0lGAe+Htdzb1mExZnfxP9IS4orCcNdWjmKV X-Received: by 2002:a50:bb26:: with SMTP id y35mr23459837ede.257.1605863467812; Fri, 20 Nov 2020 01:11:07 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1605863467; cv=none; d=google.com; s=arc-20160816; b=vI7AqlRf7w7hq+JzrNfyLJaOxonPIihS/9CoghbcOVdHwpXQEAgl5Oe+y9zikTBa3e HwBCidMnpKXztjT5P0T83Hbt0WmWveCoCg1ZH1szwDwM4vlhudUi3y9v+/uTHJfQXdSl D3StTXuDgIETEJkAtFGST9EuQk8IZ/9bXtdsgLaipt36F0RF1CoelDGD7TW6sELMCvVO Ut4b7BFfe9uzK7jxzpExaODNFwI5ciyjNOt49I5h7mTh/aXWQ5bPjDzKSvWq4i2Fr8i0 4/8Yduvhu31Y+HSY3f1AIQiEhLLCHQFHLFLfku0x4GGyBK/eeFEQReGfAhg9I6dX9+Qf JU/w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:content-language :in-reply-to:mime-version:user-agent:date:message-id:from:references :cc:to:subject; bh=sN7oV+pn/+18HO0kL851l8jPfnL/wx+pQ0WnlUPn8Bc=; b=l+ODWfvtVigc2BP2nCIxjMu1aIQUAvEMbD5mxG5H8moRpKOcXJnfuxknAyVfc6oZrW qJcHL9u9lf0N2vEDFRBEYoAB9xQl3oOVD+2Ab0RxisEgiuBrhFbloRMxEQKriBNi4GWz TGSFuIQEX5iJwCbq4A3w589/GMZ6AeoarAT/Im6UIGTI5qIV01gY4X8a8lw7xO0gSNSy 8tUT1FcVFQIxHCTpjF2Z/pRsKZMT7iDX83YCpOL3qr9ZbnITvGQEUZQlY3uzAAjTXgP+ 7e9CMOaQjZQDdyuOpHLPucbUNrgpl6MRBNSJVrnmHXxEbfap8PSecZI6S6s+1QepYYHH NDWQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id ga10si1361444ejc.686.2020.11.20.01.10.43; Fri, 20 Nov 2020 01:11:07 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727330AbgKTJJD (ORCPT + 99 others); Fri, 20 Nov 2020 04:09:03 -0500 Received: from foss.arm.com ([217.140.110.172]:45148 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726739AbgKTJJB (ORCPT ); Fri, 20 Nov 2020 04:09:01 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 1DD751042; Fri, 20 Nov 2020 01:09:01 -0800 (PST) Received: from [10.57.26.201] (unknown [10.57.26.201]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 4B85B3F70D; Fri, 20 Nov 2020 01:08:59 -0800 (PST) Subject: Re: AMU extension v1 support for cortex A76, A77, A78 CPUs To: Marc Zyngier , Neeraj Upadhyay Cc: mark.rutland@arm.com, suzuki.poulose@arm.com, ionela.voinescu@arm.com, MSM , lkml , catalin.marinas@arm.com, Will Deacon , valentin.schneider@arm.com, linux-arm-kernel@lists.infradead.org References: <2cc9dd44-0b4b-94a8-155a-7a2446a1b892@codeaurora.org> <1712842eb0767e51155a5396d282102c@kernel.org> From: Vladimir Murzin Message-ID: Date: Fri, 20 Nov 2020 09:09:00 +0000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.8.0 MIME-Version: 1.0 In-Reply-To: <1712842eb0767e51155a5396d282102c@kernel.org> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 11/20/20 8:56 AM, Marc Zyngier wrote: > On 2020-11-20 04:30, Neeraj Upadhyay wrote: >> Hi, >> >> For ARM cortex A76, A77, A78 cores (which as per TRM, support AMU) >> AA64PFR0[47:44] field is not set, and AMU does not get enabled for >> them. >> Can you please provide support for these CPUs in cpufeature.c? > > If that was the case, that'd be an erratum, and it would need to be > documented as such. It could also be that this is an optional feature > for these cores (though the TRM doesn't suggest that). > > Can someone at ARM confirm what is the expected behaviour of these CPUs? Not a confirmation, but IIRC, these are imp def features, while our cpufeatures catches architected one. Cheers Vladimir > >         M.