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Subject: Re: AMU extension v1 support for cortex A76, A77, A78 CPUs
To:     Marc Zyngier <maz@kernel.org>
Cc:     Neeraj Upadhyay <neeraju@codeaurora.org>, mark.rutland@arm.com,
        suzuki.poulose@arm.com, ionela.voinescu@arm.com,
        MSM <linux-arm-msm@vger.kernel.org>,
        lkml <linux-kernel@vger.kernel.org>, catalin.marinas@arm.com,
        Will Deacon <will@kernel.org>, valentin.schneider@arm.com,
        linux-arm-kernel@lists.infradead.org
References: <2cc9dd44-0b4b-94a8-155a-7a2446a1b892@codeaurora.org>
 <1712842eb0767e51155a5396d282102c@kernel.org>
 <e15de351-63c1-2599-82bf-22c95e8a6a62@arm.com>
 <d77713992e5abef5c6066d9f1939e8db@kernel.org>
From:   Vladimir Murzin <vladimir.murzin@arm.com>
Message-ID: <9c504d04-8d20-91cb-6284-2891589eff37@arm.com>
Date:   Fri, 20 Nov 2020 10:14:50 +0000
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On 11/20/20 9:54 AM, Marc Zyngier wrote:
> On 2020-11-20 09:09, Vladimir Murzin wrote:
>> On 11/20/20 8:56 AM, Marc Zyngier wrote:
>>> On 2020-11-20 04:30, Neeraj Upadhyay wrote:
>>>> Hi,
>>>>
>>>> For ARM cortex A76, A77, A78 cores (which as per TRM, support AMU)
>>>> AA64PFR0[47:44] field is not set, and AMU does not get enabled for
>>>> them.
>>>> Can you please provide support for these CPUs in cpufeature.c?
>>>
>>> If that was the case, that'd be an erratum, and it would need to be
>>> documented as such. It could also be that this is an optional feature
>>> for these cores (though the TRM doesn't suggest that).
>>>
>>> Can someone at ARM confirm what is the expected behaviour of these CPUs?
>>
>> Not a confirmation, but IIRC, these are imp def features, while our cpufeatures
>> catches architected one.
> 
> Ah, good point. So these CPUs implement some sort of AMU, and not *the* AMU.
> 
> Yet the register names are the same. Who thought that'd be a good idea?

IMO, it is the case where imp def has been generalized into arch extension, so
something have been moved over.

Cheers
Vladimir

> 
>         M.