Received: by 2002:a05:6a10:16a7:0:0:0:0 with SMTP id gp39csp1150735pxb; Fri, 20 Nov 2020 02:24:43 -0800 (PST) X-Google-Smtp-Source: ABdhPJwZ3kyIHJME7JC0R31OWKNGJcSMIqbU4mNHqlsHq0tJ+ymG083a9zRhe3Wf2F4rpCU1FM3x X-Received: by 2002:a17:906:e4f:: with SMTP id q15mr31623897eji.220.1605867883151; Fri, 20 Nov 2020 02:24:43 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1605867883; cv=none; d=google.com; s=arc-20160816; b=i9NzIdBzKFBhSNTNNxHFjjuA/6eGaqVJKS4P+lc7DJ0liWrWdU+x6GkwOmu4OYwnrG QV9zuUStT2QmkuG/f4QHVwxgXPW9D4vTOwGXa2LnpNMaA3BU51CFo1JVALNl6UJX+e7t 2xBTcudf9r57O10c8Lz1EaX4BdAxJ0ZNfvbROuKpljgn1UYGCu8qvZx6fW3MAHwqMeq1 FiqftHrP1pckidGcVfhXnuR03jM/Uz2CDTTCBPQwFGYxsJOvZFxc/EM7CttfttDEvb9m XrTc9pBNHnZ+0iCAQwPniPL7DqyK1x4Py/JalThdRDN+lQWM43XKCCDra5S7/wVKWkfn KweQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:user-agent:in-reply-to:content-disposition :mime-version:references:message-id:subject:cc:to:from:date; bh=Dx4gv9ywzkMQlNH/XajyWveUfHwkya4EMgWItKpXI78=; b=pa5UMEuhu+rQnbWynkAD8rtRaggPEWAlUhQX8kcVU7J/Nt2o+VitrbeP5jx/UaScjv EPxeuhhlO6Q7Qj9r+UDW9UdSu3EVE9jMkN5V/oiS2dobySQ8zeUAp0bzSoI2ya8idtFr Ge3h1fvejfXxWT4N6+YeqOnXQQo/aR1b60vic2TeHRtLnXZGXIPzxRJxvASvqje6RduD dr+X4agv0Kq7T3q1HYnjPm2LVmvupI0k4JZuOetrjyVO80meIdj0s8UrKgsDokkSghoW 4o4OR9bXlxPUyt27fs1xKQYLm3oXLbQPbOpz9epJNaVE94UsCDRORdgzZEAq8fDo9ew/ BJUw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id y4si1475332ejj.723.2020.11.20.02.24.19; Fri, 20 Nov 2020 02:24:43 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727220AbgKTKUr (ORCPT + 99 others); Fri, 20 Nov 2020 05:20:47 -0500 Received: from foss.arm.com ([217.140.110.172]:46716 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725797AbgKTKUr (ORCPT ); Fri, 20 Nov 2020 05:20:47 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 9D6EC1042; Fri, 20 Nov 2020 02:20:46 -0800 (PST) Received: from bogus (unknown [10.57.54.72]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 8D13D3F70D; Fri, 20 Nov 2020 02:20:44 -0800 (PST) Date: Fri, 20 Nov 2020 10:20:42 +0000 From: Sudeep Holla To: Marc Zyngier Cc: Neeraj Upadhyay , mark.rutland@arm.com, suzuki.poulose@arm.com, ionela.voinescu@arm.com, MSM , lkml , catalin.marinas@arm.com, Will Deacon , valentin.schneider@arm.com, linux-arm-kernel@lists.infradead.org Subject: Re: AMU extension v1 support for cortex A76, A77, A78 CPUs Message-ID: <20201120102042.25caeib3iiuxkogt@bogus> References: <2cc9dd44-0b4b-94a8-155a-7a2446a1b892@codeaurora.org> <1712842eb0767e51155a5396d282102c@kernel.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1712842eb0767e51155a5396d282102c@kernel.org> User-Agent: NeoMutt/20171215 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, Nov 20, 2020 at 08:56:31AM +0000, Marc Zyngier wrote: > On 2020-11-20 04:30, Neeraj Upadhyay wrote: > > Hi, > > > > For ARM cortex A76, A77, A78 cores (which as per TRM, support AMU) > > AA64PFR0[47:44] field is not set, and AMU does not get enabled for > > them. > > Can you please provide support for these CPUs in cpufeature.c? > > If that was the case, that'd be an erratum, and it would need to be > documented as such. It could also be that this is an optional feature > for these cores (though the TRM doesn't suggest that). > > Can someone at ARM confirm what is the expected behaviour of these CPUs? IIRC discussion with Ionela long back, we intentionally decided not to support IMPDEF(pre 8.4 non-architected so called AMUs) on the CPUs listed in $subject. -- Regards, Sudeep