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[84.226.167.205]) by smtp.googlemail.com with ESMTPSA id f25sm3671593edr.53.2020.11.22.07.16.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 22 Nov 2020 07:16:03 -0800 (PST) Date: Sun, 22 Nov 2020 16:16:02 +0100 From: Krzysztof Kozlowski To: Sylwester Nawrocki Cc: linux-clk@vger.kernel.org, tomasz.figa@gmail.com, cw00.choi@samsung.com, m.szyprowski@samsung.com, sboyd@kernel.org, mturquette@baylibre.com, b.zolnierkie@samsung.com, linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org Subject: Re: [PATCH v5] clk: samsung: Prevent potential endless loop in the PLL ops Message-ID: <20201122151602.GA5346@kozik-lap> References: <20201120155731.26898-1-s.nawrocki@samsung.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline In-Reply-To: <20201120155731.26898-1-s.nawrocki@samsung.com> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, Nov 20, 2020 at 04:57:31PM +0100, Sylwester Nawrocki wrote: > The PLL status polling loops in the set_rate callbacks of some PLLs > have no timeout detection and may become endless loops when something > goes wrong with the PLL. > > For some PLLs there is already the ktime API based timeout detection, > but it will not work in all conditions when .set_rate gets called. > In particular, before the clocksource is initialized or when the > timekeeping is suspended. > > This patch adds a common helper with the PLL status bit polling and > timeout detection. For conditions where the timekeeping API should not > be used a simple readl_relaxed/cpu_relax() busy loop is added with the > iterations limit derived from measurements of readl_relaxed() execution > time for various PLL types and Exynos SoCs variants. > > Actual PLL lock time depends on the P divider value, the VCO frequency > and a constant PLL type specific LOCK_FACTOR and can be calculated as > > lock_time = Pdiv * LOCK_FACTOR / VCO_freq > > For the ktime API use cases a common timeout value of 20 ms is applied > for all the PLLs with an assumption that maximum possible value of Pdiv > is 64, maximum possible LOCK_FACTOR value is 3000 and minimum VCO > frequency is 24 MHz. > > Signed-off-by: Sylwester Nawrocki Reviewed-by: Krzysztof Kozlowski Best regards, Krzysztof