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Date:   Mon, 23 Nov 2020 15:58:27 +0800
From:   Tingwei Zhang <tingweiz@codeaurora.org>
To:     Suzuki K Poulose <suzuki.poulose@arm.com>
Cc:     linux-arm-kernel@lists.infradead.org, anshuman.khandual@arm.com,
        coresight@lists.linaro.org, linux-kernel@vger.kernel.org,
        jonathan.zhouwen@huawei.com, mike.leach@linaro.org
Subject: Re: [PATCH v4 20/25] coresight: etm4x: Detect system instructions
 support
Message-ID: <20201123075827.GA18352@codeaurora.org>
References: <20201119164547.2982871-1-suzuki.poulose@arm.com>
 <20201119164547.2982871-21-suzuki.poulose@arm.com>
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In-Reply-To: <20201119164547.2982871-21-suzuki.poulose@arm.com>
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Hi Suzuki,

On Fri, Nov 20, 2020 at 12:45:42AM +0800, Suzuki K Poulose wrote:
> ETM v4.4 onwards adds support for system instruction access
> to the ETM. Detect the support on an ETM and switch to using the
> mode when available.
> 
> Cc: Mike Leach <mike.leach@linaro.org>
> Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org>
> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
> ---
>  .../coresight/coresight-etm4x-core.c          | 39 +++++++++++++++++++
>  1 file changed, 39 insertions(+)
> 
> diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c 
> b/drivers/hwtracing/coresight/coresight-etm4x-core.c
> index 7ac0a185c146..5cbea9c27f58 100644
> --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c
> +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c
> @@ -684,6 +684,37 @@ static const struct coresight_ops etm4_cs_ops = {
>  	.source_ops	= &etm4_source_ops,
>  };
> 
> +static inline bool cpu_supports_sysreg_trace(void)
> +{
> +	u64 dfr0 = read_sysreg_s(SYS_ID_AA64DFR0_EL1);
> +
> +	return ((dfr0 >> ID_AA64DFR0_TRACEVER_SHIFT) & 0xfUL) > 0;
> +}
> +
> +static bool etm4_init_sysreg_access(struct etmv4_drvdata *drvdata,
> +				    struct csdev_access *csa)
> +{
> +	u32 devarch;
> +
> +	if (!cpu_supports_sysreg_trace())
> +		return false;
> +
> +	/*
> +	 * ETMs implementing sysreg access must implement TRCDEVARCH.
> +	 */
> +	devarch = read_etm4x_sysreg_const_offset(TRCDEVARCH);
> +	if ((devarch & ETM_DEVARCH_ID_MASK) != ETM_DEVARCH_ETMv4x_ARCH)

Is this driver suppose to work on ETM 5.0/ETE trace unit before ETE driver
is ready?

Thanks,
Tingwei

> +		return false;
> +	*csa = (struct csdev_access) {
> +		.io_mem	= false,
> +		.read	= etm4x_sysreg_read,
> +		.write	= etm4x_sysreg_write,
> +	};
> +
> +	drvdata->arch = etm_devarch_to_arch(devarch);
> +	return true;
> +}
> +
>  static bool etm4_init_iomem_access(struct etmv4_drvdata *drvdata,
>  				   struct csdev_access *csa)
>  {
> @@ -714,9 +745,17 @@ static bool etm4_init_iomem_access(struct etmv4_drvdata 
> *drvdata,
>  static bool etm4_init_csdev_access(struct etmv4_drvdata *drvdata,
>  				   struct csdev_access *csa)
>  {
> +	/*
> +	 * Always choose the memory mapped io, if there is
> +	 * a memory map to prevent sysreg access on broken
> +	 * systems.
> +	 */
>  	if (drvdata->base)
>  		return etm4_init_iomem_access(drvdata, csa);
> 
> +	if (etm4_init_sysreg_access(drvdata, csa))
> +		return true;
> +
>  	return false;
>  }
> 
> -- 
> 2.24.1
> 
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