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From:   Yash Shah <yash.shah@openfive.com>
To:     Rob Herring <robh@kernel.org>
CC:     "Paul Walmsley ( Sifive)" <paul.walmsley@sifive.com>,
        "palmer@dabbelt.com" <palmer@dabbelt.com>,
        "aou@eecs.berkeley.edu" <aou@eecs.berkeley.edu>,
        "Jonathan.Cameron@huawei.com" <Jonathan.Cameron@huawei.com>,
        "wsa@kernel.org" <wsa@kernel.org>,
        "sam@ravnborg.org" <sam@ravnborg.org>,
        Sagar Kadam <sagar.kadam@openfive.com>,
        "anup@brainfault.org" <anup@brainfault.org>,
        "bp@suse.de" <bp@suse.de>,
        "devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
        "linux-riscv@lists.infradead.org" <linux-riscv@lists.infradead.org>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
        Sachin Ghadi <sachin.ghadi@openfive.com>
Subject: RE: [PATCH 1/2] RISC-V: Update l2 cache DT documentation to add
 support for SiFive FU740
Thread-Topic: [PATCH 1/2] RISC-V: Update l2 cache DT documentation to add
 support for SiFive FU740
Thread-Index: AQHWuNPXeVMTcgdvxUGkk0ItZFlleKnSmU6AgAL3WiA=
Date:   Mon, 23 Nov 2020 10:32:43 +0000
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References: <1605172274-44916-1-git-send-email-yash.shah@sifive.com>
 <20201121125443.GA2076465@robh.at.kernel.org>
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> -----Original Message-----
> From: Rob Herring <robh@kernel.org>
> Sent: 21 November 2020 18:25
> To: Yash Shah <yash.shah@openfive.com>
> Cc: Paul Walmsley ( Sifive) <paul.walmsley@sifive.com>;
> palmer@dabbelt.com; aou@eecs.berkeley.edu;
> Jonathan.Cameron@huawei.com; wsa@kernel.org; sam@ravnborg.org;
> Sagar Kadam <sagar.kadam@openfive.com>; anup@brainfault.org;
> bp@suse.de; devicetree@vger.kernel.org; linux-riscv@lists.infradead.org;
> linux-kernel@vger.kernel.org; Sachin Ghadi <sachin.ghadi@openfive.com>
> Subject: Re: [PATCH 1/2] RISC-V: Update l2 cache DT documentation to add
> support for SiFive FU740
>=20
> [External Email] Do not click links or attachments unless you recognize t=
he
> sender and know the content is safe
>=20
> On Thu, Nov 12, 2020 at 02:41:13PM +0530, Yash Shah wrote:
> > The L2 cache controller in SiFive FU740 has 4 ECC interrupt sources as
> > compared to 3 in FU540. Update the DT documentation accordingly with
> > "compatible" and "interrupt" property changes.
> >
> > Signed-off-by: Yash Shah <yash.shah@sifive.com>
> > ---
> >  .../devicetree/bindings/riscv/sifive-l2-cache.yaml | 33
> > +++++++++++++++++-----
> >  1 file changed, 26 insertions(+), 7 deletions(-)
> >
> > diff --git
> > a/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml
> > b/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml
> > index efc0198..4873d5c 100644
> > --- a/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml
> > +++ b/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml

<...>

> > @@ -51,12 +54,6 @@ properties:
> >
> >    cache-unified: true
> >
> > -  interrupts:
> > -    description: |
> > -      Must contain entries for DirError, DataError and DataFail signal=
s.
> > -    minItems: 3
> > -    maxItems: 3
>=20
> Keep this here and just change maxItems to 4. Really, what each interrupt=
 is
> should be listed out as an 'items' entry.
>=20

Sure will send a v2 with the above modifications.

<...>

>=20
> > +
> > +else:
> > +  properties:
> > +    interrupts:
> > +      description: |
> > +        Must contain entries for DirError, DirFail, DataError, DataFai=
l signals.
>=20
> DirFail should be last so you keep the same indices.

Actually, the interrupts have been numbered like that in FU740 SoCs and the=
 driver expects the interrupts to be in this order.
I will keep the same order for v2 as well. Let me know if you still disagre=
e.

Thanks for your review.

- Yash