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Mon, 23 Nov 2020 19:24:29 -0800 Envelope-to: nishad.saraf@xilinx.com, michal.simek@xilinx.com, wendy.liang@xilinx.com, dri-devel@lists.freedesktop.org, linux-media@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, gregkh@linuxfoundation.org, arnd@arndb.de, robh+dt@kernel.org, hdanton@sina.com Received: from [10.23.125.111] (port=58718) by smtp.xilinx.com with esmtp (Exim 4.90) (envelope-from ) id 1khOwP-000806-IM; Mon, 23 Nov 2020 19:24:29 -0800 Subject: Re: [PATCH v2 9/9] misc: xilinx-ai-engine: Add support for servicing error interrupts To: Hillf Danton , Wendy Liang CC: , , , , , , , , Nishad Saraf References: <1605743289-26575-1-git-send-email-wendy.liang@xilinx.com> <20201119083645.544-1-hdanton@sina.com> From: Wendy Liang Message-ID: <627ef0ef-5e4c-b310-92e1-a9bb57d1aa96@xilinx.com> Date: Mon, 23 Nov 2020 19:24:28 -0800 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:78.0) Gecko/20100101 Thunderbird/78.5.0 MIME-Version: 1.0 In-Reply-To: <20201119083645.544-1-hdanton@sina.com> Content-Type: text/plain; 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X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 Nov 2020 03:24:31.1521 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 92a24136-47f7-4768-ba79-08d89028753c X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c;Ip=[149.199.62.198];Helo=[xsj-pvapexch01.xlnx.xilinx.com] X-MS-Exchange-CrossTenant-AuthSource: BL2NAM02FT057.eop-nam02.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CO6PR02MB7667 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 11/19/20 12:36 AM, Hillf Danton wrote: > On Wed, 18 Nov 2020 15:48:09 -0800 Wendy Liang wrote: >> +/** >> + * aie_interrupt() - interrupt handler for AIE. >> + * @irq: Interrupt number. >> + * @data: AI engine device structure. >> + * @return: IRQ_HANDLED. >> + * >> + * This thread function disables level 2 interrupt controllers and schedules a >> + * task in workqueue to backtrack the source of error interrupt. Disabled >> + * interrupts are re-enabled after successful completion of bottom half. >> + */ >> +irqreturn_t aie_interrupt(int irq, void *data) >> +{ >> + struct aie_device *adev = data; >> + struct aie_partition *apart; >> + int ret; >> + bool sched_work = false; >> + >> + ret = mutex_lock_interruptible(&adev->mlock); >> + if (ret) { >> + dev_err(&adev->dev, >> + "Failed to acquire lock. Process was interrupted by fatal signals\n"); >> + return IRQ_NONE; >> + } >> + >> + list_for_each_entry(apart, &adev->partitions, node) { >> + struct aie_location loc; >> + u32 ttype, l2_mask, l2_status, l2_bitmap_offset = 0; >> + >> + ret = mutex_lock_interruptible(&apart->mlock); >> + if (ret) { >> + dev_err(&apart->dev, >> + "Failed to acquire lock. Process was interrupted by fatal signals\n"); >> + return IRQ_NONE; > > Though quite unlikely, you need to release adev->mlock before > going home. Thanks to point it out, I will change in next version Thanks, Wendy > >> + } >> + >> + for (loc.col = apart->range.start.col, loc.row = 0; >> + loc.col < apart->range.start.col + apart->range.size.col; >> + loc.col++) { >> + ttype = apart->adev->ops->get_tile_type(&loc); >> + if (ttype != AIE_TILE_TYPE_SHIMNOC) >> + continue; >> + >> + l2_mask = aie_get_l2_mask(apart, &loc); >> + if (l2_mask) { >> + aie_resource_cpy_from_arr32(&apart->l2_mask, >> + l2_bitmap_offset * >> + 32, &l2_mask, 32); >> + aie_disable_l2_ctrl(apart, &loc, l2_mask); >> + } >> + l2_bitmap_offset++; >> + >> + l2_status = aie_get_l2_status(apart, &loc); >> + if (l2_status) { >> + aie_clear_l2_intr(apart, &loc, l2_status); >> + sched_work = true; >> + } else { >> + aie_enable_l2_ctrl(apart, &loc, l2_mask); >> + } >> + } >> + mutex_unlock(&apart->mlock); >> + } >> + >> + /* For ES1 silicon, interrupts are latched in NPI */ >> + if (adev->version == VERSAL_ES1_REV_ID) { >> + ret = zynqmp_pm_clear_aie_npi_isr(adev->pm_node_id, >> + AIE_NPI_ERROR_ID); >> + if (ret < 0) >> + dev_err(&adev->dev, "Failed to clear NPI ISR\n"); >> + } >> + >> + mutex_unlock(&adev->mlock); >> + >> + if (sched_work) >> + schedule_work(&adev->backtrack); >> + >> + return IRQ_HANDLED; >> +}