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[23.128.96.18]) by mx.google.com with ESMTP id cz27si8055876edb.291.2020.11.23.20.21.25; Mon, 23 Nov 2020 20:21:47 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727388AbgKXESx (ORCPT + 99 others); Mon, 23 Nov 2020 23:18:53 -0500 Received: from mga11.intel.com ([192.55.52.93]:8580 "EHLO mga11.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726158AbgKXESw (ORCPT ); Mon, 23 Nov 2020 23:18:52 -0500 IronPort-SDR: awTksB35+VmSFcRp/TlgIYNJvL8gd+FmjPhXGfhHY6CaPHv5M6PGM2VEeBkpLM/RGP+DClF1jh h3lV0R1/zurw== X-IronPort-AV: E=McAfee;i="6000,8403,9814"; a="168378654" X-IronPort-AV: E=Sophos;i="5.78,365,1599548400"; d="scan'208";a="168378654" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Nov 2020 20:18:52 -0800 IronPort-SDR: xUXBDvIm1UZknpr7R2R9zdODFvqZdZH0fv+ICqO7T8LxhWheSut2XvvIcmJEDtVmjE8OEJ1elT H2rnDynyh0Bw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.78,365,1599548400"; d="scan'208";a="343029831" Received: from sgsxdev004.isng.phoenix.local (HELO localhost) ([10.226.81.179]) by orsmga002.jf.intel.com with ESMTP; 23 Nov 2020 20:18:49 -0800 From: "Ramuthevar,Vadivel MuruganX" To: broonie@kernel.org, linux-kernel@vger.kernel.org, linux-spi@vger.kernel.org Cc: linux-mtd@lists.infradead.org, vigneshr@ti.com, p.yadav@ti.com, cheol.yong.kim@intel.com, qi-ming.wu@intel.com, Ramuthevar Vadivel Murugan Subject: [PATCH v9 1/5] spi: cadence-quadspi: Add QSPI support for Intel LGM SoC Date: Tue, 24 Nov 2020 12:18:36 +0800 Message-Id: <20201124041840.31066-2-vadivel.muruganx.ramuthevar@linux.intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201124041840.31066-1-vadivel.muruganx.ramuthevar@linux.intel.com> References: <20201124041840.31066-1-vadivel.muruganx.ramuthevar@linux.intel.com> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Ramuthevar Vadivel Murugan Add QSPI controller support for Intel LGM SoC. Signed-off-by: Ramuthevar Vadivel Murugan --- drivers/spi/Kconfig | 2 +- drivers/spi/spi-cadence-quadspi.c | 3 +++ 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index d2c976e55b8b..926da61eee5a 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -203,7 +203,7 @@ config SPI_CADENCE config SPI_CADENCE_QUADSPI tristate "Cadence Quad SPI controller" - depends on OF && (ARM || ARM64 || COMPILE_TEST) + depends on OF && (ARM || ARM64 || X86 || COMPILE_TEST) help Enable support for the Cadence Quad SPI Flash controller. diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-quadspi.c index 40938cf3806d..d7b10c46fa70 100644 --- a/drivers/spi/spi-cadence-quadspi.c +++ b/drivers/spi/spi-cadence-quadspi.c @@ -1401,6 +1401,9 @@ static const struct of_device_id cqspi_dt_ids[] = { .compatible = "ti,am654-ospi", .data = &am654_ospi, }, + { + .compatible = "intel,lgm-qspi", + }, { /* end of table */ } }; -- 2.11.0