Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18;
IronPort-SDR: Hg3YCddKYDxXMjGAHbOqoamFE5167ZvFT0n/hnR7F2I2EOdaSakruv3TzJBS82yOBdcc997jRs
 1Um9p8bxXJ1w==
IronPort-SDR: dgUbOEgPz8fFz6GulRm6TvgDxeQwc+GMEHe4GtKMrz7Vd5UIGU5RqTI4H48P+i7wQ2o1BpOhhO
 X5wxo90C1J2A==
From:   matthew.gerlach@linux.intel.com
To:     linux-fpga@vger.kernel.org, linux-kernel@vger.kernel.org,
        mdf@kernel.org, hao.wu@intel.com, trix@redhat.com,
        linux-doc@vger.kernel.org, corbet@lwn.net
Cc:     Matthew Gerlach <matthew.gerlach@linux.intel.com>
Subject: [PATCH v3 0/2] fpga: dfl: optional VSEC for start of dfl
Date:   Tue, 24 Nov 2020 07:56:56 -0800
Message-Id: <20201124155658.700976-1-matthew.gerlach@linux.intel.com>
MIME-Version: 1.0
Content-Transfer-Encoding: 8bit
Precedence: bulk

From: Matthew Gerlach <matthew.gerlach@linux.intel.com>

The start of a Device Feature List (DFL) is currently assumed to be at
Bar0/Offset 0 on the PCIe bus by drivers/fpga/dfl-pci.c.  This patchset
adds support for the start one or more DFLs to be specified in a
Vendor-Specific Capability (VSEC) structure in PCIe config space.  If no
such VSEC structure exists, then the start is assumed to be
Bar0/Offset 0 for backward compatibility.

Matthew Gerlach (2):
  fpga: dfl: refactor cci_enumerate_feature_devs()
  fpga: dfl: look for vendor specific capability

 Documentation/fpga/dfl.rst |  25 ++++++
 drivers/fpga/dfl-pci.c     | 169 +++++++++++++++++++++++++++++--------
 2 files changed, 159 insertions(+), 35 deletions(-)

-- 
2.25.2