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Subject: Re: [PATCH v4] arm64: dts: qcom: sc7180: Add lpass cpu node for I2S
 driver
To:     Srinivasa Rao Mandadapu <srivasam@codeaurora.org>,
        agross@kernel.org, bjorn.andersson@linaro.org, robh+dt@kernel.org,
        linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org,
        linux-kernel@vger.kernel.org, rohitkr@codeaurora.org
Cc:     Ajit Pandey <ajitp@codeaurora.org>,
        Cheng-Yi Chiang <cychiang@chromium.org>,
        V Sujith Kumar Reddy <vsujithk@codeaurora.org>
References: <1600450426-14063-1-git-send-email-srivasam@codeaurora.org>
From:   Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Message-ID: <ad3221fb-4148-6457-05dd-3fece2677b13@linaro.org>
Date:   Mon, 30 Nov 2020 11:02:23 +0000
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On 18/09/2020 18:33, Srinivasa Rao Mandadapu wrote:
> From: Ajit Pandey <ajitp@codeaurora.org>
> 
> Add the I2S controller node to sc7180 dtsi.
> Add pinmux for primary and secondary I2S.
> 
> Signed-off-by: Ajit Pandey <ajitp@codeaurora.org>
> Signed-off-by: Cheng-Yi Chiang <cychiang@chromium.org>
> Signed-off-by: V Sujith Kumar Reddy <vsujithk@codeaurora.org>
> Signed-off-by: Srinivasa Rao Mandadapu <srivasam@codeaurora.org>
> ---

Reviewed-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>

> Changes since v3:
>     -- The typo error fix
> Changes since v2:
>     -- The plement of lpass_cpu node is changed
> Changes since v1:
>     -- Updated I2S pin control nodes  with grouping common pin controls
>     -- Updated lpass_cpu node with proper control names
> 
>   arch/arm64/boot/dts/qcom/sc7180.dtsi | 69 ++++++++++++++++++++++++++++++++++++
>   1 file changed, 69 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi
> index 6678f1e..427a4bf 100644
> --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi
> @@ -1742,6 +1742,45 @@
>   				};
>   			};
>   
> +			sec_mi2s_active: sec-mi2s-active {
> +				pinmux {
> +					pins = "gpio49", "gpio50", "gpio51";
> +					function = "mi2s_1";
> +				};
> +
> +				pinconf {
> +					pins = "gpio49", "gpio50", "gpio51";
> +					drive-strength = <8>;
> +					bias-pull-up;
> +				};
> +			};
> +
> +			pri_mi2s_active: pri-mi2s-active {
> +				pinmux {
> +					pins = "gpio53", "gpio54", "gpio55", "gpio56";
> +					function = "mi2s_0";
> +				};
> +
> +				pinconf {
> +					pins = "gpio53", "gpio54", "gpio55", "gpio56";
> +					drive-strength = <8>;
> +					bias-pull-up;
> +				};
> +			};
> +
> +			pri_mi2s_mclk_active: pri-mi2s-mclk-active {
> +				pinmux {
> +					pins = "gpio57";
> +					function = "lpass_ext";
> +				};
> +
> +				pinconf {
> +					pins = "gpio57";
> +					drive-strength = <8>;
> +					bias-pull-up;
> +				};
> +			};
> +
>   			sdc1_on: sdc1-on {
>   				pinconf-clk {
>   					pins = "sdc1_clk";
> @@ -3389,6 +3428,36 @@
>   			#power-domain-cells = <1>;
>   		};
>   
> +		lpass_cpu: lpass@62f00000 {
> +			compatible = "qcom,sc7180-lpass-cpu";
> +
> +			reg = <0 0x62f00000 0 0x29000>;
> +			reg-names = "lpass-lpaif";
> +
> +			iommus = <&apps_smmu 0x1020 0>;
> +
> +			power-domains = <&lpass_hm LPASS_CORE_HM_GDSCR>;
> +
> +			clocks = <&gcc GCC_LPASS_CFG_NOC_SWAY_CLK>,
> +				 <&lpasscc LPASS_AUDIO_CORE_CORE_CLK>,
> +				 <&lpasscc LPASS_AUDIO_CORE_EXT_MCLK0_CLK>,
> +				 <&lpasscc LPASS_AUDIO_CORE_SYSNOC_MPORT_CORE_CLK>,
> +				 <&lpasscc LPASS_AUDIO_CORE_LPAIF_PRI_IBIT_CLK>,
> +				 <&lpasscc LPASS_AUDIO_CORE_LPAIF_SEC_IBIT_CLK>;
> +
> +			clock-names = "pcnoc-sway-clk", "audio-core",
> +					"mclk0", "pcnoc-mport-clk",
> +					"mi2s-bit-clk0", "mi2s-bit-clk1";
> +
> +
> +			#sound-dai-cells = <1>;
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +
> +			interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
> +			interrupt-names = "lpass-irq-lpaif";
> +		};
> +
>   		lpass_hm: clock-controller@63000000 {
>   			compatible = "qcom,sc7180-lpasshm";
>   			reg = <0 0x63000000 0 0x28>;
>