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Date:   Mon, 30 Nov 2020 11:33:13 -0600
From:   Bjorn Helgaas <helgaas@kernel.org>
To:     Rob Herring <robh+dt@kernel.org>
Cc:     Jianjun Wang <jianjun.wang@mediatek.com>,
        Bjorn Helgaas <bhelgaas@google.com>,
        Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
        Ryder Lee <ryder.lee@mediatek.com>,
        Philipp Zabel <p.zabel@pengutronix.de>,
        Matthias Brugger <matthias.bgg@gmail.com>,
        Mauro Carvalho Chehab <mchehab+huawei@kernel.org>,
        David Miller <davem@davemloft.net>,
        PCI <linux-pci@vger.kernel.org>,
        "moderated list:ARM/Mediatek SoC support" 
        <linux-mediatek@lists.infradead.org>, devicetree@vger.kernel.org,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
        linux-arm-kernel <linux-arm-kernel@lists.infradead.org>,
        Sj Huang <sj.huang@mediatek.com>,
        Youlin Pei <youlin.pei@mediatek.com>,
        Chuanjia Liu <chuanjia.liu@mediatek.com>,
        qizhong.cheng@mediatek.com, sin_jieyang@mediatek.com
Subject: Re: [v4,2/3] PCI: mediatek: Add new generation controller support
Message-ID: <20201130173313.GA1089760@bjorn-Precision-5520>
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On Mon, Nov 30, 2020 at 09:05:48AM -0700, Rob Herring wrote:
> On Sun, Nov 22, 2020 at 11:45 PM Jianjun Wang <jianjun.wang@mediatek.com> wrote:
> > On Thu, 2020-11-19 at 14:28 -0600, Bjorn Helgaas wrote:
> > > "Add new generation" really contains no information.  And "mediatek"
> > > is already used for the pcie-mediatek.c driver, so we should have a
> > > new tag for this new driver.  Include useful information in the
> > > subject, e.g.,
> > >
> > >   PCI: mediatek-gen3: Add MediaTek Gen3 driver for MT8192

> > > > +   writel(PCIE_CFG_HEADER_FORCE_BE(devfn, bus->number, bytes),
> > > > +          port->base + PCIE_CFGNUM_REG);
> > > > +
> > > > +   *val = readl(port->base + PCIE_CFG_OFFSET_ADDR + (where & ~0x3));
> > >
> > > These look like they need to be atomic, since you need a writel()
> > > followed by a readl().
> > >
> > > pci_lock_config() (used in pci_bus_read_config_*(), etc) uses the
> > > global pci_lock for this unless CONFIG_PCI_LOCKLESS_CONFIG is set.
> > >
> > > But I would like to eventually move away from this implicit dependency
> > > on pci_lock.  If you need to make this atomic, can you add the
> > > explicit locking here, so there's a clear connection between the lock
> > > and the things it protects?
> >
> > Sure, I will split it to a map_bus() function and use the standard
> > pci_generic_config_read32/write32 functions as Rob's suggestion. I think
> > the potential risks of atomic read/write can be avoided.
> 
> The generic functions have no effect on atomicity, but using them does
> make it easier to find the non-atomic cases.
> 
> I'm not sure that having host drivers do their own locking is the best
> approach. That's a recipe for more cleanups. It's a common enough
> issue that I think it's better if we have locking done in 1 place.
> Then host drivers can simply say if they need locking or not via some
> bus flag.

Yeah, you may be right.  I guess we don't have to make it an issue for
this patch; we do have pci_lock that protects this, whether the
write/read occurs in the driver or in
pci_generic_config_read32/write32.

Bjorn