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Date:   Mon, 30 Nov 2020 15:25:47 -0700
From:   Rob Herring <robh@kernel.org>
To:     Sia Jee Heng <jee.heng.sia@intel.com>
Cc:     vkoul@kernel.org, Eugeniy.Paltsev@synopsys.com,
        andriy.shevchenko@linux.intel.com, dmaengine@vger.kernel.org,
        linux-kernel@vger.kernel.org, devicetree@vger.kernel.org
Subject: Re: [PATCH v5 01/16] dt-bindings: dma: Add YAML schemas for
 dw-axi-dmac
Message-ID: <20201130222547.GA3123716@robh.at.kernel.org>
References: <20201123023452.7894-1-jee.heng.sia@intel.com>
 <20201123023452.7894-2-jee.heng.sia@intel.com>
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On Mon, Nov 23, 2020 at 10:34:37AM +0800, Sia Jee Heng wrote:
> YAML schemas Device Tree (DT) binding is the new format for DT to replace
> the old format. Introduce YAML schemas DT binding for dw-axi-dmac and
> remove the old version.
> 
> Signed-off-by: Sia Jee Heng <jee.heng.sia@intel.com>
> ---
>  .../bindings/dma/snps,dw-axi-dmac.txt         |  39 ------
>  .../bindings/dma/snps,dw-axi-dmac.yaml        | 126 ++++++++++++++++++
>  2 files changed, 126 insertions(+), 39 deletions(-)
>  delete mode 100644 Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.txt
>  create mode 100644 Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml
> 
> diff --git a/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.txt b/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.txt
> deleted file mode 100644
> index dbe160400adc..000000000000
> --- a/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.txt
> +++ /dev/null
> @@ -1,39 +0,0 @@
> -Synopsys DesignWare AXI DMA Controller
> -
> -Required properties:
> -- compatible: "snps,axi-dma-1.01a"
> -- reg: Address range of the DMAC registers. This should include
> -  all of the per-channel registers.
> -- interrupt: Should contain the DMAC interrupt number.
> -- dma-channels: Number of channels supported by hardware.
> -- snps,dma-masters: Number of AXI masters supported by the hardware.
> -- snps,data-width: Maximum AXI data width supported by hardware.
> -  (0 - 8bits, 1 - 16bits, 2 - 32bits, ..., 6 - 512bits)
> -- snps,priority: Priority of channel. Array size is equal to the number of
> -  dma-channels. Priority value must be programmed within [0:dma-channels-1]
> -  range. (0 - minimum priority)
> -- snps,block-size: Maximum block size supported by the controller channel.
> -  Array size is equal to the number of dma-channels.
> -
> -Optional properties:
> -- snps,axi-max-burst-len: Restrict master AXI burst length by value specified
> -  in this property. If this property is missing the maximum AXI burst length
> -  supported by DMAC is used. [1:256]
> -
> -Example:
> -
> -dmac: dma-controller@80000 {
> -	compatible = "snps,axi-dma-1.01a";
> -	reg = <0x80000 0x400>;
> -	clocks = <&core_clk>, <&cfgr_clk>;
> -	clock-names = "core-clk", "cfgr-clk";
> -	interrupt-parent = <&intc>;
> -	interrupts = <27>;
> -
> -	dma-channels = <4>;
> -	snps,dma-masters = <2>;
> -	snps,data-width = <3>;
> -	snps,block-size = <4096 4096 4096 4096>;
> -	snps,priority = <0 1 2 3>;
> -	snps,axi-max-burst-len = <16>;
> -};
> diff --git a/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml b/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml
> new file mode 100644
> index 000000000000..6c2e8e612af5
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml
> @@ -0,0 +1,126 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/dma/snps,dw-axi-dmac.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Synopsys DesignWare AXI DMA Controller
> +
> +maintainers:
> +  - Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com
> +
> +description: |

Don't need '|' unless there's formatting to preserve.

> + Synopsys DesignWare AXI DMA Controller DT Binding

And should be 2 space indent.

> +
> +properties:
> +  compatible:
> +    enum:
> +      - snps,axi-dma-1.01a
> +
> +  reg:
> +    items:
> +      - description: Address range of the DMAC registers

Just 'maxItems: 1'

> +
> +  reg-names:
> +    items:
> +      - const: axidma_ctrl_regs
> +
> +  interrupts:
> +    maxItems: 1
> +
> +  clocks:
> +    items:
> +      - description: Bus Clock
> +      - description: Module Clock
> +
> +  clock-names:
> +    items:
> +      - const: core-clk
> +      - const: cfgr-clk
> +
> +  '#dma-cells':
> +    const: 1
> +
> +  dma-channels:
> +    description: |
> +      Number of channels supported by hardware.

No need to describe a common property. You do need to provide some 
constraints. I'd assume there's less than 2^32 channels.

> +
> +  snps,dma-masters:
> +    description: |
> +      Number of AXI masters supported by the hardware.
> +    allOf:

You don't need to use allOf with a $ref anymore.

> +      - $ref: /schemas/types.yaml#/definitions/uint32
> +      - enum: [1, 2]
> +        default: 2
> +
> +  snps,data-width:
> +    description: |
> +      AXI data width supported by hardware.
> +      (0 - 8bits, 1 - 16bits, 2 - 32bits, ..., 6 - 512bits)
> +    allOf:
> +      - $ref: /schemas/types.yaml#/definitions/uint32
> +      - enum: [0, 1, 2, 3, 4, 5, 6]
> +        default: 4
> +
> +  snps,priority:
> +    description: |
> +      Channel priority specifier associated with the DMA channels.
> +    allOf:
> +      - $ref: /schemas/types.yaml#/definitions/uint32-array
> +      - minItems: 1
> +        maxItems: 8
> +        default: [0, 1, 2, 3]
> +
> +  snps,block-size:
> +    description: |
> +      Channel block size specifier associated with the DMA channels.
> +    allOf:
> +      - $ref: /schemas/types.yaml#/definitions/uint32-array
> +      - minItems: 1
> +        maxItems: 8
> +        default: [4096, 4096, 4096, 4096]
> +
> +  snps,axi-max-burst-len:
> +    description: |
> +      Restrict master AXI burst length by value specified in this property.
> +      If this property is missing the maximum AXI burst length supported by
> +      DMAC is used. [1:256]

Looks like some constraints.

> +    allOf:
> +      - $ref: /schemas/types.yaml#/definitions/uint32
> +        default: 16
> +
> +required:
> +  - compatible
> +  - reg
> +  - clocks
> +  - clock-names
> +  - interrupts
> +  - '#dma-cells'
> +  - dma-channels
> +  - snps,dma-masters
> +  - snps,data-width
> +  - snps,priority
> +  - snps,block-size
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +     #include <dt-bindings/interrupt-controller/arm-gic.h>
> +     #include <dt-bindings/interrupt-controller/irq.h>
> +     /* example with snps,dw-axi-dmac */
> +     dmac: dma-controller@80000 {
> +         compatible = "snps,axi-dma-1.01a";
> +         reg = <0x80000 0x400>;
> +         clocks = <&core_clk>, <&cfgr_clk>;
> +         clock-names = "core-clk", "cfgr-clk";
> +         interrupt-parent = <&intc>;
> +         interrupts = <27>;
> +         #dma-cells = <1>;
> +         dma-channels = <4>;
> +         snps,dma-masters = <2>;
> +         snps,data-width = <3>;
> +         snps,block-size = <4096 4096 4096 4096>;
> +         snps,priority = <0 1 2 3>;
> +         snps,axi-max-burst-len = <16>;
> +     };
> -- 
> 2.18.0
>