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Date:   Tue, 1 Dec 2020 17:51:35 +0000
From:   Mark Brown <broonie@kernel.org>
To:     Srinivasa Rao Mandadapu <srivasam@codeaurora.org>
Cc:     agross@kernel.org, bjorn.andersson@linaro.org, lgirdwood@gmail.com,
        robh+dt@kernel.org, plai@codeaurora.org, bgoswami@codeaurora.org,
        perex@perex.cz, tiwai@suse.com, srinivas.kandagatla@linaro.org,
        rohitkr@codeaurora.org, linux-arm-msm@vger.kernel.org,
        alsa-devel@alsa-project.org, devicetree@vger.kernel.org,
        linux-kernel@vger.kernel.org,
        V Sujith Kumar Reddy <vsujithk@codeaurora.org>
Subject: Re: [PATCH v4 1/2] Partially revert ASoC: qcom: Fix enabling BCLK
 and LRCLK in LPAIF invalid state
Message-ID: <20201201175135.GO5239@sirena.org.uk>
References: <1606539559-4277-1-git-send-email-srivasam@codeaurora.org>
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 <20201130124617.GC4756@sirena.org.uk>
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On Tue, Dec 01, 2020 at 11:01:21PM +0530, Srinivasa Rao Mandadapu wrote:
> On 11/30/2020 6:16 PM, Mark Brown wrote:

> > Part of this commit message says that the problem was making the regist=
ers
> > non-volatile but both the change and the rest of the commit message say
> > that the issue was that the registers were made volatile.  I'm also
> > still unclear as to what the issue is either way - how does reading the
> > state of the registers from the hardware instead of the cache affect
> > things?

> Initial problem was, during playback if device suspended, I2S and DMA
> control registers

> are getting reset and unable to recover playback after resume.

> As these registers were non volatile registers, driver is not getting act=
ual
> register value

> and unable to report error state to application. Due to this application

> keeps on polling for HW current pointer state and not exited from PCM
> running state.

> Later from review comments by Srinivas kandagatla, I got to know
>=20
> about regcache sync APIs, which can be used=A0 to sync cache after resume=
 and
>=20
> HW registers can be updated with=A0 original values. With that playback c=
an be
> continued.
>=20
> So is the reason, I am reverting partial changes in the commit b182496822=
1c.

I don't understand why a fix for the register cache not being in sync
with the hardware doesn't involve syncing the register cache with the
hardware.

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