Received: by 2002:a05:6a10:f347:0:0:0:0 with SMTP id d7csp997066pxu; Wed, 2 Dec 2020 08:30:59 -0800 (PST) X-Google-Smtp-Source: ABdhPJxrroHk4pQixgDKbtKXFToZXJgOMmHtgfWSxggykEnVKylD0goUEdut2l3cvdjb176Bvg4d X-Received: by 2002:aa7:cdd8:: with SMTP id h24mr685718edw.153.1606926659141; Wed, 02 Dec 2020 08:30:59 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1606926659; cv=none; d=google.com; s=arc-20160816; b=aTGdz0hsTViNkSWoTCTDI0PCynrZx/R+KmGwuZWmHACCUpe/ael3nbQxvM0ZhIjUdz QHuf6heHegTXWLLiGb/xSmHgQWHedUU3smb4oT7zflcbJfgMwN9HPPtEwlfs2M2DjxSE B1ywyheWlCM/dPv/iBK9FqurIcd0R6Lrjp11HGjczw6foAvrPwX7eonob19DXgQ0O9+9 PAPGix+ieVru3+F5ChqqVS0IVokHMx/cysL1z8zRqlYP1OQ09B5uX0TNqmn0wdLJdDL5 n+Ka19KX6idJQkU00ZPxNeWQX2PQOWPl4k3k4pXM04oiykcpnAZHb2p/3B/ZEq0CfQ7U wLdQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=KBCNB+Sc4AIn5nSUp36oH4crDRiPD9a2uVN6w6/FbAc=; b=wY1Q4b8QPrjUmzevDl2VRVGHMntgThEr1LgW+eSDVT0HaX/dgYhUia2Ya9mpAbn43R RuseMHZlR5LWrD5KmRiqf3NjNccc7UuAdNjdks6y8mKGq9sq5y8pzbc1QQJyf7NByhvc NBP60PIHFys6Fs1kqWflVxHR4fjZuHQJ3Y2jyK0ntezwtvqAg8xPvhsNnbmH8TaL1YbW 394zI/ynIa9FvXLoVyM45defVM83Lf2trjZAZ6X93d2UCdij5jDeVs+lmtRwy1e1r7VS E+ClHmoBpRuYwB1vVnsm5+/yCEuP7xCpyw6U9t/se4F7t8xKOP/nL5yhkyNmLizVEnKH LxpA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=siol.net Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id a16si292946eda.189.2020.12.02.08.30.34; Wed, 02 Dec 2020 08:30:59 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=siol.net Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728666AbgLBQ1n (ORCPT + 99 others); Wed, 2 Dec 2020 11:27:43 -0500 Received: from mailoutvs15.siol.net ([185.57.226.206]:54050 "EHLO mail.siol.net" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1728079AbgLBQ1n (ORCPT ); Wed, 2 Dec 2020 11:27:43 -0500 Received: from localhost (localhost [127.0.0.1]) by mail.siol.net (Postfix) with ESMTP id 9FED7520F73; Wed, 2 Dec 2020 17:26:54 +0100 (CET) X-Virus-Scanned: amavisd-new at psrvmta11.zcs-production.pri Received: from mail.siol.net ([127.0.0.1]) by localhost (psrvmta11.zcs-production.pri [127.0.0.1]) (amavisd-new, port 10032) with ESMTP id 3XvSBcOwSiDx; Wed, 2 Dec 2020 17:26:53 +0100 (CET) Received: from mail.siol.net (localhost [127.0.0.1]) by mail.siol.net (Postfix) with ESMTPS id 68888520F70; Wed, 2 Dec 2020 17:26:53 +0100 (CET) Received: from kista.localnet (cpe1-5-97.cable.triera.net [213.161.5.97]) (Authenticated sender: jernej.skrabec@siol.net) by mail.siol.net (Postfix) with ESMTPA id E4642520F54; Wed, 2 Dec 2020 17:26:52 +0100 (CET) From: Jernej =?utf-8?B?xaBrcmFiZWM=?= To: Maxime Ripard , Chen-Yu Tsai , Andre Przywara Cc: Icenowy Zheng , linux-arm-kernel@lists.infradead.org, linux-sunxi@googlegroups.com, Linus Walleij , Rob Herring , Yangtao Li , linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Andre Przywara Subject: Re: [PATCH 7/8] arm64: dts: allwinner: Add Allwinner H616 .dtsi file Date: Wed, 02 Dec 2020 17:33:04 +0100 Message-ID: <8978273.D0rJ4KIVhu@kista> In-Reply-To: <20201202135409.13683-8-andre.przywara@arm.com> References: <20201202135409.13683-1-andre.przywara@arm.com> <20201202135409.13683-8-andre.przywara@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: 7Bit Content-Type: text/plain; charset="us-ascii" Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Dne sreda, 02. december 2020 ob 14:54:08 CET je Andre Przywara napisal(a): > This (relatively) new SoC is similar to the H6, but drops the (broken) > PCIe support and the USB 3.0 controller. It also gets the management > controller removed, which in turn removes *some*, but not all of the > devices formerly dedicated to the ARISC (CPUS). > There does not seem to be an external interrupt controller anymore, so > no external interrupts through an NMI pin. The AXP driver needs to learn > living with that. > > Signed-off-by: Andre Przywara > --- > .../arm64/boot/dts/allwinner/sun50i-h616.dtsi | 704 ++++++++++++++++++ > 1 file changed, 704 insertions(+) > create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi > > diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi b/arch/arm64/ boot/dts/allwinner/sun50i-h616.dtsi > new file mode 100644 > index 000000000000..dcffbfdcd26b > --- /dev/null > +++ b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi > @@ -0,0 +1,704 @@ > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) > +// Copyright (C) 2020 Arm Ltd. > +// based on the H6 dtsi, which is: > +// Copyright (C) 2017 Icenowy Zheng > + > +#include > +#include > +#include > +#include > +#include > + > +/ { > + interrupt-parent = <&gic>; > + #address-cells = <2>; > + #size-cells = <2>; > + > + cpus { > + #address-cells = <1>; > + #size-cells = <0>; > + > + cpu0: cpu@0 { > + compatible = "arm,cortex-a53"; > + device_type = "cpu"; > + reg = <0>; > + enable-method = "psci"; > + clocks = <&ccu CLK_CPUX>; > + }; > + > + cpu1: cpu@1 { > + compatible = "arm,cortex-a53"; > + device_type = "cpu"; > + reg = <1>; > + enable-method = "psci"; > + clocks = <&ccu CLK_CPUX>; > + }; > + > + cpu2: cpu@2 { > + compatible = "arm,cortex-a53"; > + device_type = "cpu"; > + reg = <2>; > + enable-method = "psci"; > + clocks = <&ccu CLK_CPUX>; > + }; > + > + cpu3: cpu@3 { > + compatible = "arm,cortex-a53"; > + device_type = "cpu"; > + reg = <3>; > + enable-method = "psci"; > + clocks = <&ccu CLK_CPUX>; > + }; > + }; > + > + reserved-memory { > + #address-cells = <2>; > + #size-cells = <2>; > + ranges; > + > + /* 512KiB reserved for ARM Trusted Firmware (BL31) */ > + secmon_reserved: secmon@40000000 { > + reg = <0x0 0x40000000 0x0 0x80000>; > + no-map; > + }; > + }; > + > + osc24M: osc24M_clk { > + #clock-cells = <0>; > + compatible = "fixed-clock"; > + clock-frequency = <24000000>; > + clock-output-names = "osc24M"; > + }; > + > + pmu { > + compatible = "arm,cortex-a53-pmu"; > + interrupts = , > + , > + , > + ; > + interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; > + }; > + > + psci { > + compatible = "arm,psci-0.2"; > + method = "smc"; > + }; > + > + timer { > + compatible = "arm,armv8-timer"; > + arm,no-tick-in-suspend; > + interrupts = + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, > + + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, > + + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, > + + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; > + }; > + > + soc { > + compatible = "simple-bus"; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0x0 0x0 0x0 0x40000000>; > + > + syscon: syscon@3000000 { > + compatible = "allwinner,sun50i-h616-system- control", > + "allwinner,sun50i-a64-system- control"; Those H616 is not compatible to A64 one because it has second emac control register at offset 0x34, which no other supported SoC has. > + reg = <0x03000000 0x1000>; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges; > + > + sram_c: sram@28000 { > + compatible = "mmio-sram"; > + reg = <0x00028000 0x30000>; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0 0x00028000 0x30000>; > + }; > + > + sram_c1: sram@1a00000 { > + compatible = "mmio-sram"; > + reg = <0x01a00000 0x200000>; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0 0x01a00000 0x200000>; > + > + ve_sram: sram-section@0 { > + compatible = "allwinner,sun50i-h616-sram-c1", > + "allwinner,sun4i-a10-sram-c1"; > + reg = <0x000000 0x200000>; > + }; > + }; > + }; > + > + ccu: clock@3001000 { > + compatible = "allwinner,sun50i-h616-ccu"; > + reg = <0x03001000 0x1000>; > + clocks = <&osc24M>, <&rtc 0>, <&rtc 2>; > + clock-names = "hosc", "losc", "iosc"; > + #clock-cells = <1>; > + #reset-cells = <1>; > + }; > + > + watchdog: watchdog@30090a0 { > + compatible = "allwinner,sun50i-h616-wdt", > + "allwinner,sun6i-a31-wdt"; > + reg = <0x030090a0 0x20>; > + interrupts = ; > + clocks = <&osc24M>; > + status = "disabled"; > + }; > + > + pio: pinctrl@300b000 { > + compatible = "allwinner,sun50i-h616-pinctrl"; > + reg = <0x0300b000 0x400>; > + interrupts = , > + , > + , > + , > + ; > + clocks = <&ccu CLK_APB1>, <&osc24M>, <&rtc 0>; > + clock-names = "apb", "hosc", "losc"; > + gpio-controller; > + #gpio-cells = <3>; > + interrupt-controller; > + #interrupt-cells = <3>; > + > + ext_rgmii_pins: rgmii-pins { > + pins = "PI0", "PI1", "PI2", "PI3", "PI4", > + "PI5", "PI7", "PI8", "PI9", "PI10", > + "PI11", "PI12", "PI13", "PI14", "PI15", > + "PI16"; > + function = "emac0"; > + drive-strength = <40>; > + }; > + > + i2c0_pins: i2c0-pins { > + pins = "PI6", "PI7"; > + function = "i2c0"; > + }; > + > + i2c3_pins_a: i2c1-pins-a { > + pins = "PH4", "PH5"; > + function = "i2c3"; > + }; > + > + ir_rx_pin: ir_rx_pin { > + pins = "PH10"; > + function = "ir_rx"; > + }; > + > + mmc0_pins: mmc0-pins { > + pins = "PF0", "PF1", "PF2", "PF3", > + "PF4", "PF5"; > + function = "mmc0"; > + drive-strength = <30>; > + bias-pull-up; > + }; > + > + mmc1_pins: mmc1-pins { > + pins = "PG0", "PG1", "PG2", "PG3", > + "PG4", "PG5"; > + function = "mmc1"; > + drive-strength = <30>; > + bias-pull-up; > + }; > + > + mmc2_pins: mmc2-pins { > + pins = "PC0", "PC1", "PC5", "PC6", > + "PC8", "PC9", "PC10", "PC11", > + "PC13", "PC14", "PC15", "PC16"; > + function = "mmc2"; > + drive-strength = <30>; > + bias-pull-up; > + }; > + > + spi0_pins: spi0-pins { > + pins = "PC0", "PC2", "PC3", "PC4"; > + function = "spi0"; > + }; > + > + spi1_pins: spi1-pins { > + pins = "PH6", "PH7", "PH8"; > + function = "spi1"; > + }; > + > + spi1_cs_pin: spi1-cs-pin { > + pins = "PH5"; > + function = "spi1"; > + }; > + > + uart0_ph_pins: uart0-ph-pins { > + pins = "PH0", "PH1"; > + function = "uart0"; > + }; > + > + uart1_pins: uart1-pins { > + pins = "PG6", "PG7"; > + function = "uart1"; > + }; > + > + uart1_rts_cts_pins: uart1-rts-cts-pins { > + pins = "PG8", "PG9"; > + function = "uart1"; > + }; > + }; > + > + gic: interrupt-controller@3021000 { > + compatible = "arm,gic-400"; > + reg = <0x03021000 0x1000>, > + <0x03022000 0x2000>, > + <0x03024000 0x2000>, > + <0x03026000 0x2000>; > + interrupts = ; > + interrupt-controller; > + #interrupt-cells = <3>; > + }; > + > + mmc0: mmc@4020000 { > + compatible = "allwinner,sun50i-h616-mmc", > + "allwinner,sun50i-a100-mmc"; > + reg = <0x04020000 0x1000>; > + clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>; > + clock-names = "ahb", "mmc"; > + resets = <&ccu RST_BUS_MMC0>; > + reset-names = "ahb"; > + interrupts = ; > + pinctrl-names = "default"; > + pinctrl-0 = <&mmc0_pins>; > + status = "disabled"; > + #address-cells = <1>; > + #size-cells = <0>; > + }; > + > + mmc1: mmc@4021000 { > + compatible = "allwinner,sun50i-h616-mmc", > + "allwinner,sun50i-a100-mmc"; > + reg = <0x04021000 0x1000>; > + clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>; > + clock-names = "ahb", "mmc"; > + resets = <&ccu RST_BUS_MMC1>; > + reset-names = "ahb"; > + interrupts = ; > + pinctrl-names = "default"; > + pinctrl-0 = <&mmc1_pins>; > + status = "disabled"; > + #address-cells = <1>; > + #size-cells = <0>; > + }; > + > + mmc2: mmc@4022000 { > + compatible = "allwinner,sun50i-h616-emmc", > + "allwinner,sun50i-a64-emmc"; > + reg = <0x04022000 0x1000>; > + clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>; > + clock-names = "ahb", "mmc"; > + resets = <&ccu RST_BUS_MMC2>; > + reset-names = "ahb"; > + interrupts = ; > + pinctrl-names = "default"; > + pinctrl-0 = <&mmc2_pins>; > + status = "disabled"; > + #address-cells = <1>; > + #size-cells = <0>; > + }; I would skip mmc1 and mmc2, as they were not proved to be working yet. > + > + uart0: serial@5000000 { > + compatible = "snps,dw-apb-uart"; > + reg = <0x05000000 0x400>; > + interrupts = ; > + reg-shift = <2>; > + reg-io-width = <4>; > + clocks = <&ccu CLK_BUS_UART0>; > + resets = <&ccu RST_BUS_UART0>; > + status = "disabled"; > + }; > + > + uart1: serial@5000400 { > + compatible = "snps,dw-apb-uart"; > + reg = <0x05000400 0x400>; > + interrupts = ; > + reg-shift = <2>; > + reg-io-width = <4>; > + clocks = <&ccu CLK_BUS_UART1>; > + resets = <&ccu RST_BUS_UART1>; > + status = "disabled"; > + }; > + > + uart2: serial@5000800 { > + compatible = "snps,dw-apb-uart"; > + reg = <0x05000800 0x400>; > + interrupts = ; > + reg-shift = <2>; > + reg-io-width = <4>; > + clocks = <&ccu CLK_BUS_UART2>; > + resets = <&ccu RST_BUS_UART2>; > + status = "disabled"; > + }; > + > + uart3: serial@5000c00 { > + compatible = "snps,dw-apb-uart"; > + reg = <0x05000c00 0x400>; > + interrupts = ; > + reg-shift = <2>; > + reg-io-width = <4>; > + clocks = <&ccu CLK_BUS_UART3>; > + resets = <&ccu RST_BUS_UART3>; > + status = "disabled"; > + }; > + > + uart4: serial@5001000 { > + compatible = "snps,dw-apb-uart"; > + reg = <0x05001000 0x400>; > + interrupts = ; > + reg-shift = <2>; > + reg-io-width = <4>; > + clocks = <&ccu CLK_BUS_UART4>; > + resets = <&ccu RST_BUS_UART4>; > + status = "disabled"; > + }; > + > + uart5: serial@5001400 { > + compatible = "snps,dw-apb-uart"; > + reg = <0x05001400 0x400>; > + interrupts = ; > + reg-shift = <2>; > + reg-io-width = <4>; > + clocks = <&ccu CLK_BUS_UART5>; > + resets = <&ccu RST_BUS_UART5>; > + status = "disabled"; > + }; > + > + i2c0: i2c@5002000 { > + compatible = "allwinner,sun50i-h616-i2c", > + "allwinner,sun6i-a31-i2c"; > + reg = <0x05002000 0x400>; > + interrupts = ; > + clocks = <&ccu CLK_BUS_I2C0>; > + resets = <&ccu RST_BUS_I2C0>; > + pinctrl-names = "default"; > + pinctrl-0 = <&i2c0_pins>; > + status = "disabled"; > + #address-cells = <1>; > + #size-cells = <0>; > + }; > + > + i2c1: i2c@5002400 { > + compatible = "allwinner,sun50i-h616-i2c", > + "allwinner,sun6i-a31-i2c"; > + reg = <0x05002400 0x400>; > + interrupts = ; > + clocks = <&ccu CLK_BUS_I2C1>; > + resets = <&ccu RST_BUS_I2C1>; > + status = "disabled"; > + #address-cells = <1>; > + #size-cells = <0>; > + }; > + > + i2c2: i2c@5002800 { > + compatible = "allwinner,sun50i-h616-i2c", > + "allwinner,sun6i-a31-i2c"; > + reg = <0x05002800 0x400>; > + interrupts = ; > + clocks = <&ccu CLK_BUS_I2C2>; > + resets = <&ccu RST_BUS_I2C2>; > + status = "disabled"; > + #address-cells = <1>; > + #size-cells = <0>; > + }; > + > + i2c3: i2c@5002c00 { > + compatible = "allwinner,sun50i-h616-i2c", > + "allwinner,sun6i-a31-i2c"; > + reg = <0x05002c00 0x400>; > + interrupts = ; > + clocks = <&ccu CLK_BUS_I2C3>; > + resets = <&ccu RST_BUS_I2C3>; > + status = "disabled"; > + #address-cells = <1>; > + #size-cells = <0>; > + }; > + > + i2c4: i2c@5003000 { > + compatible = "allwinner,sun50i-h616-i2c", > + "allwinner,sun6i-a31-i2c"; > + reg = <0x05003000 0x400>; > + interrupts = ; > + clocks = <&ccu CLK_BUS_I2C4>; > + resets = <&ccu RST_BUS_I2C4>; > + status = "disabled"; > + #address-cells = <1>; > + #size-cells = <0>; > + }; > + > + spi0: spi@5010000 { > + compatible = "allwinner,sun50i-h616-spi", > + "allwinner,sun8i-h3-spi"; > + reg = <0x05010000 0x1000>; > + interrupts = ; > + clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>; > + clock-names = "ahb", "mod"; > + resets = <&ccu RST_BUS_SPI0>; > + pinctrl-names = "default"; > + pinctrl-0 = <&spi0_pins>; > + status = "disabled"; > + #address-cells = <1>; > + #size-cells = <0>; > + }; > + > + spi1: spi@5011000 { > + compatible = "allwinner,sun50i-h616-spi", > + "allwinner,sun8i-h3-spi"; > + reg = <0x05011000 0x1000>; > + interrupts = ; > + clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>; > + clock-names = "ahb", "mod"; > + resets = <&ccu RST_BUS_SPI1>; > + pinctrl-names = "default"; > + pinctrl-0 = <&spi1_pins>; > + status = "disabled"; > + #address-cells = <1>; > + #size-cells = <0>; > + }; > + > + emac0: ethernet@5020000 { > + compatible = "allwinner,sun50i-h616-emac", > + "allwinner,sun50i-a64-emac"; > + syscon = <&syscon>; > + reg = <0x05020000 0x10000>; > + interrupts = ; > + interrupt-names = "macirq"; > + resets = <&ccu RST_BUS_EMAC0>; > + reset-names = "stmmaceth"; > + clocks = <&ccu CLK_BUS_EMAC0>; > + clock-names = "stmmaceth"; > + status = "disabled"; > + > + mdio: mdio { > + compatible = "snps,dwmac-mdio"; > + #address-cells = <1>; > + #size-cells = <0>; > + }; > + }; > + > + usbotg: usb@5100000 { > + compatible = "allwinner,sun50i-h616-musb", > + "allwinner,sun8i-a33-musb"; > + reg = <0x05100000 0x0400>; > + clocks = <&ccu CLK_BUS_OTG>; > + resets = <&ccu RST_BUS_OTG>; > + interrupts = ; > + interrupt-names = "mc"; > + phys = <&usbphy 0>; > + phy-names = "usb"; > + extcon = <&usbphy 0>; > + status = "disabled"; > + }; > + > + usbphy: phy@5100400 { > + compatible = "allwinner,sun50i-h616-usb-phy"; > + reg = <0x05100400 0x24>, > + <0x05101800 0x4>, > + <0x05200800 0x4>, > + <0x05310800 0x4>, > + <0x05311800 0x4>; > + reg-names = "phy_ctrl", > + "pmu0", > + "pmu1", > + "pmu2", > + "pmu3"; > + clocks = <&ccu CLK_USB_PHY0>, > + <&ccu CLK_USB_PHY1>, > + <&ccu CLK_USB_PHY2>, > + <&ccu CLK_USB_PHY3>; > + clock-names = "usb0_phy", > + "usb1_phy", > + "usb2_phy", > + "usb3_phy"; > + resets = <&ccu RST_USB_PHY0>, > + <&ccu RST_USB_PHY1>, > + <&ccu RST_USB_PHY2>, > + <&ccu RST_USB_PHY3>; > + reset-names = "usb0_reset", > + "usb1_reset", > + "usb2_reset", > + "usb3_reset"; > + status = "disabled"; > + #phy-cells = <1>; > + }; > + > + ehci0: usb@5101000 { > + compatible = "allwinner,sun50i-h616-ehci", > + "generic-ehci"; > + reg = <0x05101000 0x100>; > + interrupts = ; > + clocks = <&ccu CLK_BUS_OHCI0>, > + <&ccu CLK_BUS_EHCI0>, > + <&ccu CLK_USB_OHCI0>; > + resets = <&ccu RST_BUS_OHCI0>, > + <&ccu RST_BUS_EHCI0>; > + status = "disabled"; > + }; > + > + ohci0: usb@5101400 { > + compatible = "allwinner,sun50i-h616-ohci", > + "generic-ohci"; > + reg = <0x05101400 0x100>; > + interrupts = ; > + clocks = <&ccu CLK_BUS_OHCI0>, > + <&ccu CLK_USB_OHCI0>; > + resets = <&ccu RST_BUS_OHCI0>; > + status = "disabled"; > + }; > + > + ehci1: usb@5200000 { > + compatible = "allwinner,sun50i-h616-ehci", > + "generic-ehci"; > + reg = <0x05200000 0x100>; > + interrupts = ; > + clocks = <&ccu CLK_BUS_OHCI1>, > + <&ccu CLK_BUS_EHCI1>, > + <&ccu CLK_USB_OHCI1>; > + resets = <&ccu RST_BUS_OHCI1>, > + <&ccu RST_BUS_EHCI1>; > + phys = <&usbphy 1>; > + phy-names = "usb"; > + status = "disabled"; > + }; > + > + ohci1: usb@5200400 { > + compatible = "allwinner,sun50i-h616-ohci", > + "generic-ohci"; > + reg = <0x05200400 0x100>; > + interrupts = ; > + clocks = <&ccu CLK_BUS_OHCI1>, > + <&ccu CLK_USB_OHCI1>; > + resets = <&ccu RST_BUS_OHCI1>; > + phys = <&usbphy 1>; > + phy-names = "usb"; > + status = "disabled"; > + }; > + > + ehci2: usb@5310000 { > + compatible = "allwinner,sun50i-h616-ehci", > + "generic-ehci"; > + reg = <0x05310000 0x100>; > + interrupts = ; > + clocks = <&ccu CLK_BUS_OHCI2>, > + <&ccu CLK_BUS_EHCI2>, > + <&ccu CLK_USB_OHCI2>; > + resets = <&ccu RST_BUS_OHCI2>, > + <&ccu RST_BUS_EHCI2>; > + phys = <&usbphy 2>; > + phy-names = "usb"; > + status = "disabled"; > + }; > + > + ohci2: usb@5310400 { > + compatible = "allwinner,sun50i-h616-ohci", > + "generic-ohci"; > + reg = <0x05310400 0x100>; > + interrupts = ; > + clocks = <&ccu CLK_BUS_OHCI2>, > + <&ccu CLK_USB_OHCI2>; > + resets = <&ccu RST_BUS_OHCI2>; > + phys = <&usbphy 2>; > + phy-names = "usb"; > + status = "disabled"; > + }; > + > + ehci3: usb@5311000 { > + compatible = "allwinner,sun50i-h616-ehci", > + "generic-ehci"; > + reg = <0x05311000 0x100>; > + interrupts = ; > + clocks = <&ccu CLK_BUS_OHCI3>, > + <&ccu CLK_BUS_EHCI3>, > + <&ccu CLK_USB_OHCI3>; > + resets = <&ccu RST_BUS_OHCI3>, > + <&ccu RST_BUS_EHCI3>; > + phys = <&usbphy 3>; > + phy-names = "usb"; > + status = "disabled"; > + }; > + > + ohci3: usb@5311400 { > + compatible = "allwinner,sun50i-h616-ohci", > + "generic-ohci"; > + reg = <0x05311400 0x100>; > + interrupts = ; > + clocks = <&ccu CLK_BUS_OHCI3>, > + <&ccu CLK_USB_OHCI3>; > + resets = <&ccu RST_BUS_OHCI3>; > + phys = <&usbphy 3>; > + phy-names = "usb"; > + status = "disabled"; > + }; > + > + rtc: rtc@7000000 { > + compatible = "allwinner,sun50i-h616-rtc", > + "allwinner,sun50i-h6-rtc"; > + reg = <0x07000000 0x400>; > + interrupts = , > + ; > + clock-output-names = "osc32k", "osc32k-out", "iosc"; > + #clock-cells = <1>; > + }; > + > + r_ccu: clock@7010000 { > + compatible = "allwinner,sun50i-h616-r-ccu"; > + reg = <0x07010000 0x400>; > + clocks = <&osc24M>, <&rtc 0>, <&rtc 2>, > + <&ccu CLK_PLL_PERIPH0>; > + clock-names = "hosc", "losc", "iosc", "pll- periph"; > + #clock-cells = <1>; > + #reset-cells = <1>; > + }; > + > + r_pio: pinctrl@7022000 { > + compatible = "allwinner,sun50i-h616-r- pinctrl"; > + reg = <0x07022000 0x400>; > + interrupts = ; > + clocks = <&r_ccu CLK_R_APB1>, <&osc24M>, <&rtc 0>; > + clock-names = "apb", "hosc", "losc"; > + gpio-controller; > + #gpio-cells = <3>; > + interrupt-controller; > + #interrupt-cells = <3>; > + > + r_i2c_pins: r-i2c-pins { > + pins = "PL0", "PL1"; > + function = "s_i2c"; > + }; > + }; > + > + ir: ir@7040000 { > + compatible = "allwinner,sun50i- h616-ir", > + "allwinner,sun6i- a31-ir"; > + reg = <0x07040000 0x400>; > + interrupts = ; > + clocks = <&ccu CLK_R_APB1_IR>, > + <&ccu CLK_IR>; Above clocks and reset below should reference r_ccu. Maybe we should call clock CLK_R_IR to know it comes from second clock controller? Best regards, Jernej > + clock-names = "apb", "ir"; > + resets = <&ccu RST_R_APB1_IR>; > + pinctrl-names = "default"; > + pinctrl-0 = <&ir_rx_pin>; > + status = "disabled"; > + }; > + > + r_i2c: i2c@7081400 { > + compatible = "allwinner,sun50i-h616-i2c", > + "allwinner,sun6i-a31-i2c"; > + reg = <0x07081400 0x400>; > + interrupts = ; > + clocks = <&r_ccu CLK_R_APB2_I2C>; > + resets = <&r_ccu RST_R_APB2_I2C>; > + status = "disabled"; > + #address-cells = <1>; > + #size-cells = <0>; > + }; > + }; > +}; > -- > 2.17.5 > >