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[23.128.96.18]) by mx.google.com with ESMTP id cf10si306016ejb.454.2020.12.02.09.46.35; Wed, 02 Dec 2020 09:46:58 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@broadcom.com header.s=google header.b=ADX2L6rx; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=broadcom.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730936AbgLBRoZ (ORCPT + 99 others); Wed, 2 Dec 2020 12:44:25 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44830 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730931AbgLBRoZ (ORCPT ); Wed, 2 Dec 2020 12:44:25 -0500 Received: from mail-pl1-x641.google.com (mail-pl1-x641.google.com [IPv6:2607:f8b0:4864:20::641]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 271C8C0613D4 for ; Wed, 2 Dec 2020 09:43:45 -0800 (PST) Received: by mail-pl1-x641.google.com with SMTP id r2so1535671pls.3 for ; Wed, 02 Dec 2020 09:43:45 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=broadcom.com; s=google; h=subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to; bh=iAf9bcWd7xmsTJepiNxesuticr7+ogCP7zDgAIfwsik=; b=ADX2L6rxKOeuhsuCg9AaITlZP/1mMUrpaNeNIDCv5owZqeo02QQlDcqnAGh9tp928B LbJiZG8T8YaJeGoul7ZQj4Y+fLhxlEAtfyN7dGcftKcwaJDDuKxpRB/F5WnSnD9NCmJt RdvVg7Nu5h2Yfu8/rz+MzfHsEkQ7sNi5PGx2U= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:to:cc:references:from:message-id:date :user-agent:mime-version:in-reply-to; bh=iAf9bcWd7xmsTJepiNxesuticr7+ogCP7zDgAIfwsik=; b=V2dTvokvf+1hla1GhBXqzRmYZZzfLNK06HKweu85ed4L1pShYklh0WgxeSo4RG3YOi 7BLV8U0zpEecjZwHMRB+Bx63R/GDa32mfNWpu58pc2DLyeteyTI5YO7S2BOp1oKbrwJw 3jFDkfqxu3aBWc0T8Kmjt87wuVLPiz+WFpTHlCYxfP6R+ArcD0V3hpQvANb/JqySv/hs 2nrdDP0ZvAi5+qGTaDmRGkoz0olpHA6zHHMYDnRiKzoC9koBGZ9VNN5c5inwRca0ZVwN Np20CjNPaYWmFUl0ZmwDA3MzXecFPQSmKRpO3INwq40GwgnnyZzN2zqZXGOugChZ5/Xd HwOA== X-Gm-Message-State: AOAM5301MGqQEUVMhyFtXRC7aDvnWzs+uIUXfJp0KK72eVV9xsjZzez1 P5bxVP9RZo0YMueI/LG4cZLr1Q== X-Received: by 2002:a17:90a:d801:: with SMTP id a1mr951358pjv.90.1606931024333; Wed, 02 Dec 2020 09:43:44 -0800 (PST) Received: from [10.230.2.165] ([192.19.228.250]) by smtp.gmail.com with ESMTPSA id f92sm279705pjk.54.2020.12.02.09.43.41 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 02 Dec 2020 09:43:42 -0800 (PST) Subject: Re: [PATCH v3 5/6] i2c: iproc: handle master read request To: Rayagonda Kokatanur , Dhananjay Phadke Cc: Andy Shevchenko , BCM Kernel Feedback , Brendan Higgins , Florian Fainelli , linux-arm Mailing List , linux-i2c , Linux Kernel Mailing List , Lori Hikichi , Ray Jui , Scott Branden , Wolfram Sang References: <38a23afc-57da-a01f-286c-15f8b3d61705@broadcom.com> <1605316659-3422-1-git-send-email-dphadke@linux.microsoft.com> From: Ray Jui Message-ID: <23732970-d454-2655-48cd-ccaed3f8484b@broadcom.com> Date: Wed, 2 Dec 2020 09:43:38 -0800 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:78.0) Gecko/20100101 Thunderbird/78.4.3 MIME-Version: 1.0 In-Reply-To: Content-Type: multipart/signed; protocol="application/pkcs7-signature"; micalg=sha-256; boundary="000000000000eba64b05b57ec8a1" Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org --000000000000eba64b05b57ec8a1 Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit On 11/19/2020 9:59 PM, Rayagonda Kokatanur wrote: > Hi Ray and Dhananjay, > > All review comments are scattered now, please let me know what has to be > done further, > Are we going to change the tasklet to irq thread ? It really depends on the time it takes to read data out of the FIFO. Dhananjay pointed out that your comment indicates reading 10 bytes of data takes 20 us, i.e., 2 us per byte read. Do you know why it took so long? The APB bus should be a lot faster than that (in the hundreds of ns range). I am making the assumption that by the time when you try to read data out of the FIFO, the data is of course already in the FIFO, so it's not like you are waiting for data from the I2C bus and I cannot understand why it took this long. > Are we going to remove batching 64 packets if transaction > 64B and use > rx fifo threshold ? > I don't see any issue with batching. It's more efficient and less context switch overhead. > I don't see any issue with current code but if it has to change we need > a valid reason for the same. I think we need to confirm the exact time it takes to fetch data from FIFO. Once that's done, we can make a decision between keeping the tasklet based approach vs irq thread. Thanks. > If nothing to be done, please acknowledge the patch. >   > Best regards, > Raygonda > > > On Sat, Nov 14, 2020 at 6:47 AM Dhananjay Phadke > > wrote: > > On Tue, 10 Nov 2020 11:24:36 -0800, Ray Jui wrote: > > >>>> Yes it's true that for master write-read events both > >>>> IS_S_RD_EVENT_SHIFT and IS_S_RX_EVENT_SHIFT  are coming together. > >>>> So before the slave starts transmitting data to the master, it > should > >>>> first read all data from rx-fifo i.e. complete master write and > then > >>>> process master read. > >>>> > >>>> To minimise interrupt overhead, we are batching 64bytes. > >>>> To keep isr running for less time, we are using a tasklet. > >>>> Again to keep the tasklet not running for more than 20u, we > have set > >>>> max of 10 bytes data read from rx-fifo per tasklet run. > >>>> > >>>> If we start processing everything in isr and using rx threshold > >>>> interrupt, then isr will run for a longer time and this may hog the > >>>> system. > >>>> For example, to process 10 bytes it takes 20us, to process 30 > bytes it > >>>> takes 60us and so on. > >>>> So is it okay to run isr for so long ? > >>>> > >>>> Keeping all this in mind we thought a tasklet would be a good > option > >>>> and kept max of 10 bytes read per tasklet. > >>>> > >>>> Please let me know if you still feel we should not use a > tasklet and > >>>> don't batch 64 bytes. > >>> > >>> Deferring to tasklet is OK, could use a kernel thread (i.e. > threaded_irq) > >>> as i2c rate is quite low. > >>> > > > >kernel thread was proposed in the internal review. I don't see much > >benefit of using tasklet. If a thread is blocked from running for more > >than several tenth of ms, that's really a system-level issue than an > >issue with this driver. > > > >IMO, it's an overkill to use tasklet here but we can probably leave it > >as it is since it does not have a adverse effect and the code ran in > >tasklet is short. > > > >How much time is expected to read 64 bytes from an RX FIFO? Even with > >APB bus each register read is expected to be in the tenth or > hundreds of > >nanosecond range. Reading the entire FIFO of 64 bytes should take less > >than 10 us. The interrupt context switch overhead is probably longer > >than that. It's much more effective to read all of them in a single > >batch than breaking them into multiple batches. > > OK, there's a general discussions towards removing tasklets, if this > fix works with threaded isr, strongly recommend that route. > > This comment in the code suggested that register reads take long time to > drain 64 bytes. > > >+/* > >+ * It takes ~18us to reading 10bytes of data, hence to keep tasklet > >+ * running for less time, max slave read per tasklet is set to 10 > >bytes. > > @Rayagonda, please take care of hand-off mentioned below, once the > tasklet > is scheduled, isr should just return and clear status at the end of > tasklet. > > >> > >> Few other comments - > >> > >>> +              /* schedule tasklet to read data later */ > >>> +              tasklet_schedule(&iproc_i2c->slave_rx_tasklet); > >>> + > >>> +              /* clear only IS_S_RX_EVENT_SHIFT interrupt */ > >>> +              iproc_i2c_wr_reg(iproc_i2c, IS_OFFSET, > >>> +                               BIT(IS_S_RX_EVENT_SHIFT)); > >>> +      } > >> > >> Why clearing one rx interrupt bit here after scheduling tasklet? > Should all that > >> be done by tasklet? Also should just return after scheduling tasklet? > > Regards, > Dhananjay > --000000000000eba64b05b57ec8a1 Content-Type: application/pkcs7-signature; name="smime.p7s" Content-Transfer-Encoding: base64 Content-Disposition: attachment; filename="smime.p7s" Content-Description: S/MIME Cryptographic Signature MIIQMwYJKoZIhvcNAQcCoIIQJDCCECACAQExDzANBglghkgBZQMEAgEFADALBgkqhkiG9w0BBwGg gg2IMIIE6DCCA9CgAwIBAgIOSBtqCRO9gCTKXSLwFPMwDQYJKoZIhvcNAQELBQAwTDEgMB4GA1UE CxMXR2xvYmFsU2lnbiBSb290IENBIC0gUjMxEzARBgNVBAoTCkdsb2JhbFNpZ24xEzARBgNVBAMT Ckdsb2JhbFNpZ24wHhcNMTYwNjE1MDAwMDAwWhcNMjQwNjE1MDAwMDAwWjBdMQswCQYDVQQGEwJC RTEZMBcGA1UEChMQR2xvYmFsU2lnbiBudi1zYTEzMDEGA1UEAxMqR2xvYmFsU2lnbiBQZXJzb25h bFNpZ24gMiBDQSAtIFNIQTI1NiAtIEczMIIBIjANBgkqhkiG9w0BAQEFAAOCAQ8AMIIBCgKCAQEA tpZok2X9LAHsYqMNVL+Ly6RDkaKar7GD8rVtb9nw6tzPFnvXGeOEA4X5xh9wjx9sScVpGR5wkTg1 fgJIXTlrGESmaqXIdPRd9YQ+Yx9xRIIIPu3Jp/bpbiZBKYDJSbr/2Xago7sb9nnfSyjTSnucUcIP ZVChn6hKneVGBI2DT9yyyD3PmCEJmEzA8Y96qT83JmVH2GaPSSbCw0C+Zj1s/zqtKUbwE5zh8uuZ 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