Received: by 2002:a05:6a10:f347:0:0:0:0 with SMTP id d7csp444926pxu; Thu, 3 Dec 2020 04:26:51 -0800 (PST) X-Google-Smtp-Source: ABdhPJxur2K/qqZoNwEtAxLUWAKMDyREYskDKJUynCfIUMwIxYgNTbpm8kpDl+SprFrFwFMCZaY4 X-Received: by 2002:a50:ff05:: with SMTP id a5mr2597060edu.43.1606998411393; Thu, 03 Dec 2020 04:26:51 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1606998411; cv=none; d=google.com; s=arc-20160816; b=SYz+NagxzAmGWuao85SPT8YaX1og5/N5WNjvKvA5E4F8xpnYnydBxTQD8lLAjrtAn8 iq3LhxKDzFFfT+GYoFFtGQWGyIZffEp0jP82IXf5KNJN7KLW2OMWJs2/+12lyU8RXGJe FJjRKBKdrfsL2mauTgZWoILrqJzMHD+izaK9AnA9gShAdlYlOnb2Kzv3E4XC/JgDpJNH FZVTAGHJcQAZne47REbJZZN4LL34malNJqIhrPzQiWJe+q394ambUjrXLzMXkJlmNx7q l3+Xo3Kz2g6qmyxoPS0qjl4qWa3eg3lTGgiBjzg/wdRvreHNFQIolJdWna4eVctmD+sB 366g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=hwWHMBFUC6V9/7F96c3qaqAiCO5QS/z++3lsLqV/LRA=; b=vUafgXVAlcpVp7xWHj89YeY5OqbGA1E1JA5JwXalV17BjTn8mtCOVCf5zfPIg8KHV6 qpWaydD9tu2il0yyvUYZK+M5DfVDr+O7orAqwHMn2AZWRztsjV1MjL68Gtqkk7sTZB2O 2sDKa3W5KRZ2+VQHUsj9O6SqvC0xHrG+na27DOSidXyFyiSer2GNo2HOPOdaKH0F+Mxr TGOsA7Si4G5wjxB955gtJOjxSCaWWuKi91PaZIGAh7wKuWyYsU0MM1X7u+422YfDYq6r GeFsZb9udvT4Ow0sADEVUxo+CvEBJeCO7djxSy3XAfSez/dhki+Zjx1tFes4ek84F4NC kQ8w== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id u17si816747edv.131.2020.12.03.04.26.28; Thu, 03 Dec 2020 04:26:51 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2388863AbgLCMWD (ORCPT + 99 others); Thu, 3 Dec 2020 07:22:03 -0500 Received: from szxga04-in.huawei.com ([45.249.212.190]:8623 "EHLO szxga04-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2388810AbgLCMWC (ORCPT ); Thu, 3 Dec 2020 07:22:02 -0500 Received: from DGGEMS406-HUB.china.huawei.com (unknown [172.30.72.59]) by szxga04-in.huawei.com (SkyGuard) with ESMTP id 4Cmw0d6T1hz15Wyd; Thu, 3 Dec 2020 20:20:49 +0800 (CST) Received: from huawei.com (10.174.186.236) by DGGEMS406-HUB.china.huawei.com (10.3.19.206) with Microsoft SMTP Server id 14.3.487.0; Thu, 3 Dec 2020 20:21:07 +0800 From: Yifei Jiang To: , , , , , CC: , , , , , , , , , Yifei Jiang Subject: [PATCH RFC 2/3] RISC-V: KVM: Support dynamic time frequency from userspace Date: Thu, 3 Dec 2020 20:18:38 +0800 Message-ID: <20201203121839.308-3-jiangyifei@huawei.com> X-Mailer: git-send-email 2.26.2.windows.1 In-Reply-To: <20201203121839.308-1-jiangyifei@huawei.com> References: <20201203121839.308-1-jiangyifei@huawei.com> MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Type: text/plain X-Originating-IP: [10.174.186.236] X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This patch implements KVM_S/GET_ONE_REG of time frequency to support setting dynamic time frequency from userspace. When the time frequency specified by userspace is inconsistent with host 'riscv_timebase', it will use scale_mult and scale_shift to calculate guest scaling time. Signed-off-by: Yifei Jiang Signed-off-by: Yipeng Yin --- arch/riscv/include/asm/kvm_vcpu_timer.h | 9 ++++++ arch/riscv/kvm/vcpu_timer.c | 40 +++++++++++++++++++++---- 2 files changed, 44 insertions(+), 5 deletions(-) diff --git a/arch/riscv/include/asm/kvm_vcpu_timer.h b/arch/riscv/include/asm/kvm_vcpu_timer.h index 87e00d878999..41b5503de9e4 100644 --- a/arch/riscv/include/asm/kvm_vcpu_timer.h +++ b/arch/riscv/include/asm/kvm_vcpu_timer.h @@ -12,6 +12,10 @@ #include struct kvm_guest_timer { + u64 frequency; + bool need_scale; + u64 scale_mult; + u64 scale_shift; /* Time delta value */ u64 time_delta; }; @@ -38,4 +42,9 @@ int kvm_riscv_vcpu_timer_reset(struct kvm_vcpu *vcpu); void kvm_riscv_vcpu_timer_restore(struct kvm_vcpu *vcpu); int kvm_riscv_guest_timer_init(struct kvm *kvm); +static inline bool kvm_riscv_need_scale(struct kvm_guest_timer *gt) +{ + return gt->need_scale; +} + #endif diff --git a/arch/riscv/kvm/vcpu_timer.c b/arch/riscv/kvm/vcpu_timer.c index f6b35180199a..2d203660a7e9 100644 --- a/arch/riscv/kvm/vcpu_timer.c +++ b/arch/riscv/kvm/vcpu_timer.c @@ -15,9 +15,38 @@ #include #include +#define SCALE_SHIFT_VALUE 48 +#define SCALE_TOLERANCE_HZ 1000 + +static void kvm_riscv_set_time_freq(struct kvm_guest_timer *gt, u64 freq) +{ + /* + * Guest time frequency and Host time frequency are identical + * if the error between them is limited within SCALE_TOLERANCE_HZ. + */ + u64 diff = riscv_timebase > freq ? + riscv_timebase - freq : freq - riscv_timebase; + gt->need_scale = (diff >= SCALE_TOLERANCE_HZ); + if (gt->need_scale) { + gt->scale_shift = SCALE_SHIFT_VALUE; + gt->scale_mult = mul_u64_u32_div(1ULL << gt->scale_shift, + freq, riscv_timebase); + } + gt->frequency = freq; +} + +static u64 kvm_riscv_scale_time(struct kvm_guest_timer *gt, u64 time) +{ + if (kvm_riscv_need_scale(gt)) + return mul_u64_u64_shr(time, gt->scale_mult, gt->scale_shift); + + return time; +} + static u64 kvm_riscv_current_cycles(struct kvm_guest_timer *gt) { - return get_cycles64() + gt->time_delta; + u64 host_time = get_cycles64(); + return kvm_riscv_scale_time(gt, host_time) + gt->time_delta; } static u64 kvm_riscv_delta_cycles2ns(u64 cycles, @@ -33,7 +62,7 @@ static u64 kvm_riscv_delta_cycles2ns(u64 cycles, cycles_delta = cycles - cycles_now; else cycles_delta = 0; - delta_ns = mul_u64_u64_div_u64(cycles_delta, NSEC_PER_SEC, riscv_timebase); + delta_ns = mul_u64_u64_div_u64(cycles_delta, NSEC_PER_SEC, gt->frequency); local_irq_restore(flags); return delta_ns; @@ -106,7 +135,7 @@ int kvm_riscv_vcpu_get_reg_timer(struct kvm_vcpu *vcpu, switch (reg_num) { case KVM_REG_RISCV_TIMER_REG(frequency): - reg_val = riscv_timebase; + reg_val = gt->frequency; break; case KVM_REG_RISCV_TIMER_REG(time): reg_val = kvm_riscv_current_cycles(gt); @@ -150,10 +179,10 @@ int kvm_riscv_vcpu_set_reg_timer(struct kvm_vcpu *vcpu, switch (reg_num) { case KVM_REG_RISCV_TIMER_REG(frequency): - ret = -EOPNOTSUPP; + kvm_riscv_set_time_freq(gt, reg_val); break; case KVM_REG_RISCV_TIMER_REG(time): - gt->time_delta = reg_val - get_cycles64(); + gt->time_delta = reg_val - kvm_riscv_scale_time(gt, get_cycles64()); break; case KVM_REG_RISCV_TIMER_REG(compare): t->next_cycles = reg_val; @@ -219,6 +248,7 @@ int kvm_riscv_guest_timer_init(struct kvm *kvm) struct kvm_guest_timer *gt = &kvm->arch.timer; gt->time_delta = -get_cycles64(); + gt->frequency = riscv_timebase; return 0; } -- 2.19.1