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[23.128.96.18]) by mx.google.com with ESMTP id j8si831694edh.512.2020.12.03.04.59.41; Thu, 03 Dec 2020 05:00:05 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@nvidia.com header.s=n1 header.b=U0O6Uf4H; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=nvidia.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730594AbgLCM5m (ORCPT + 99 others); Thu, 3 Dec 2020 07:57:42 -0500 Received: from hqnvemgate25.nvidia.com ([216.228.121.64]:16395 "EHLO hqnvemgate25.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730563AbgLCM5l (ORCPT ); Thu, 3 Dec 2020 07:57:41 -0500 Received: from hqmail.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate25.nvidia.com (using TLS: TLSv1.2, AES256-SHA) id ; Thu, 03 Dec 2020 04:57:00 -0800 Received: from [10.25.75.116] (10.124.1.5) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Thu, 3 Dec 2020 12:56:50 +0000 Subject: Re: [PATCH V4 2/6] PCI: tegra: Map configuration space as nGnRnE To: Thierry Reding CC: "lorenzo.pieralisi@arm.com" , "robh+dt@kernel.org" , "bhelgaas@google.com" , Jonathan Hunter , "amanharitsh123@gmail.com" , "dinghao.liu@zju.edu.cn" , "kw@linux.com" , "linux-pci@vger.kernel.org" , "linux-tegra@vger.kernel.org" , "linux-kernel@vger.kernel.org" , Krishna Thota , Manikanta Maddireddy , "sagar.tv@gmail.com" References: <20201109171937.28326-1-vidyas@nvidia.com> <20201109171937.28326-3-vidyas@nvidia.com> From: Vidya Sagar Message-ID: Date: Thu, 3 Dec 2020 18:26:46 +0530 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:78.0) Gecko/20100101 Thunderbird/78.4.2 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset="windows-1252"; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit X-Originating-IP: [10.124.1.5] X-ClientProxiedBy: HQMAIL111.nvidia.com (172.20.187.18) To HQMAIL107.nvidia.com (172.20.187.13) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1607000220; bh=n6Q1Iq8q+gYcIzMJQwIa1nPLvmmTFkNyl7Hkc2iQziY=; h=Subject:To:CC:References:From:Message-ID:Date:User-Agent: MIME-Version:In-Reply-To:Content-Type:Content-Language: Content-Transfer-Encoding:X-Originating-IP:X-ClientProxiedBy; b=U0O6Uf4HWJsHuzsN2bV/Dfgn1Q1qYeAYGeT/zWqDXH5Cn37wg0C0XQ0jELSYILpnN FU0loNp9T7lKlDPwcrvTsWzHGLL7IJDPz9gVeHOGplPj7jlS75FPWFhMNDHDT21kz3 fXF22JQgBa2kD3gZSl9GjegNFZj1zGnbhoXWmSPLhnrH90QBGF6jR22T6GN9UGSRG2 By+8AFmR/HgpHyGuri6Oq5C0JVl8Y1IMWRF1mEQvEbOhvJA1rI+vuvQrrDbQDbLueZ eyou36V1ZFOhnLFE1FpoGNYTtRWN6TwmmPMEoEtOdzFmKvjUrGO8N2NSFwVZGXu/oA zRUo9+TAFjy6A== Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org > -----Original Message----- > From: Thierry Reding > Sent: Thursday, November 26, 2020 5:04 PM > To: Vidya Sagar > Cc: lorenzo.pieralisi@arm.com; robh+dt@kernel.org; bhelgaas@google.com; > Jonathan Hunter ; amanharitsh123@gmail.com; > dinghao.liu@zju.edu.cn; kw@linux.com; linux-pci@vger.kernel.org; linux- > tegra@vger.kernel.org; linux-kernel@vger.kernel.org; Krishna Thota > ; Manikanta Maddireddy ; > sagar.tv@gmail.com > Subject: Re: [PATCH V4 2/6] PCI: tegra: Map configuration space as nGnRnE > > On Mon, Nov 09, 2020 at 10:49:33PM +0530, Vidya Sagar wrote: > > As specified in the comment for pci_remap_cfgspace() define in > > arch/arm64/include/asm/io.h file, PCIe configuration space should be > > mapped as nGnRnE. Hence changing to dev_pci_remap_cfgspace() from > > devm_ioremap_resource() for mapping DBI space as that is nothing but > > the root port's own configuration space. > > > > Signed-off-by: Vidya Sagar > > --- > > V4: > > * None > > > > V3: > > * None > > > > V2: > > * Changed 'Strongly Ordered' to 'nGnRnE' > > > > drivers/pci/controller/dwc/pcie-tegra194.c | 4 +++- > > 1 file changed, 3 insertions(+), 1 deletion(-) > > > > diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c > > b/drivers/pci/controller/dwc/pcie-tegra194.c > > index b172b1d49713..7a0c64436861 100644 > > --- a/drivers/pci/controller/dwc/pcie-tegra194.c > > +++ b/drivers/pci/controller/dwc/pcie-tegra194.c > > @@ -2108,7 +2108,9 @@ static int tegra_pcie_dw_probe(struct > platform_device *pdev) > > } > > pcie->dbi_res = dbi_res; > > > > - pci->dbi_base = devm_ioremap_resource(dev, dbi_res); > > + pci->dbi_base = devm_pci_remap_cfgspace(dev, > > + dbi_res->start, > > + resource_size(dbi_res)); > > if (IS_ERR(pci->dbi_base)) > > return PTR_ERR(pci->dbi_base); > > > > Similarly to patch 1/6, this is no longer required because it's already part of one > of Rob's earlier patches, so this, too, can be dropped. Yes. This patch is not required now. I'll drop it from the next patch series. Thanks, Vidya Sagar > > Thierry