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Subject: Re: [linux-sunxi] Re: [PATCH 4/8] clk: sunxi-ng: Add support for the Allwinner H616 R-CCU
To:     andre.przywara@arm.com,
        =?ISO-8859-1?Q?Andr=E9_Przywara?= <andre.przywara@arm.com>,
        Maxime Ripard <mripard@kernel.org>,
        Chen-Yu Tsai <wens@csie.org>,
        Jernej Skrabec <jernej.skrabec@siol.net>
CC:     Icenowy Zheng <icenowy@aosc.xyz>,
        linux-arm-kernel@lists.infradead.org, linux-sunxi@googlegroups.com,
        Linus Walleij <linus.walleij@linaro.org>,
        Rob Herring <robh+dt@kernel.org>,
        Yangtao Li <frank@allwinnertech.com>,
        linux-kernel@vger.kernel.org,
        Michael Turquette <mturquette@baylibre.com>,
        Stephen Boyd <sboyd@kernel.org>,
        Philipp Zabel <p.zabel@pengutronix.de>,
        linux-clk@vger.kernel.org
From:   Icenowy Zheng <icenowy@aosc.io>
Message-ID: <52FEC187-169E-4B97-9A71-6C0E844FFCE0@aosc.io>
Precedence: bulk


=E4=BA=8E 2020=E5=B9=B412=E6=9C=883=E6=97=A5 GMT+08:00 =E4=B8=8B=E5=8D=887=
:07:02, "Andr=C3=A9 Przywara" <andre=2Eprzywara@arm=2Ecom> =E5=86=99=E5=88=
=B0:
>On 02/12/2020 14:31, Icenowy Zheng wrote:
>
>Hi,
>
>> =E4=BA=8E 2020=E5=B9=B412=E6=9C=882=E6=97=A5 GMT+08:00 =E4=B8=8B=E5=8D=
=889:54:05, Andre Przywara
><andre=2Eprzywara@arm=2Ecom> =E5=86=99=E5=88=B0:
>>> The clocks itself are identical to the H6 R-CCU, it's just that the
>>> H616
>>> has not all of them implemented (or connected)=2E
>>=20
>> For selective clocks, try to follow the practice of V3(s) driver?
>
>Not sure what you mean, isn't that what I do? Having a separate
>sunxi_ccu_desc for each SoC and referencing separate structs? At least
>that's what I see in ccu-sun8i-v3s=2Ec=2E
>
>What am I missing?

Sorry, I misred it=2E

Ignore my disturbance=2E

>
>Cheers,
>Andre
>
>>>
>>> Signed-off-by: Andre Przywara <andre=2Eprzywara@arm=2Ecom>
>>> ---
>>> drivers/clk/sunxi-ng/ccu-sun50i-h6-r=2Ec | 47
>+++++++++++++++++++++++++-
>>> drivers/clk/sunxi-ng/ccu-sun50i-h6-r=2Eh |  3 +-
>>> 2 files changed, 48 insertions(+), 2 deletions(-)
>>>
>>> diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-h6-r=2Ec
>>> b/drivers/clk/sunxi-ng/ccu-sun50i-h6-r=2Ec
>>> index 50f8d1bc7046=2E=2E119d1797f501 100644
>>> --- a/drivers/clk/sunxi-ng/ccu-sun50i-h6-r=2Ec
>>> +++ b/drivers/clk/sunxi-ng/ccu-sun50i-h6-r=2Ec
>>> @@ -136,6 +136,15 @@ static struct ccu_common
>*sun50i_h6_r_ccu_clks[] =3D
>>> {
>>> 	&w1_clk=2Ecommon,
>>> };
>>>
>>> +static struct ccu_common *sun50i_h616_r_ccu_clks[] =3D {
>>> +	&r_apb1_clk=2Ecommon,
>>> +	&r_apb2_clk=2Ecommon,
>>> +	&r_apb1_twd_clk=2Ecommon,
>>> +	&r_apb2_i2c_clk=2Ecommon,
>>> +	&r_apb1_ir_clk=2Ecommon,
>>> +	&ir_clk=2Ecommon,
>>> +};
>>> +
>>> static struct clk_hw_onecell_data sun50i_h6_r_hw_clks =3D {
>>> 	=2Ehws	=3D {
>>> 		[CLK_AR100]		=3D &ar100_clk=2Ecommon=2Ehw,
>>> @@ -152,7 +161,20 @@ static struct clk_hw_onecell_data
>>> sun50i_h6_r_hw_clks =3D {
>>> 		[CLK_IR]		=3D &ir_clk=2Ecommon=2Ehw,
>>> 		[CLK_W1]		=3D &w1_clk=2Ecommon=2Ehw,
>>> 	},
>>> -	=2Enum	=3D CLK_NUMBER,
>>> +	=2Enum	=3D CLK_NUMBER_H616,
>>> +};
>>> +
>>> +static struct clk_hw_onecell_data sun50i_h616_r_hw_clks =3D {
>>> +	=2Ehws	=3D {
>>> +		[CLK_R_AHB]		=3D &r_ahb_clk=2Ehw,
>>> +		[CLK_R_APB1]		=3D &r_apb1_clk=2Ecommon=2Ehw,
>>> +		[CLK_R_APB2]		=3D &r_apb2_clk=2Ecommon=2Ehw,
>>> +		[CLK_R_APB1_TWD]	=3D &r_apb1_twd_clk=2Ecommon=2Ehw,
>>> +		[CLK_R_APB2_I2C]	=3D &r_apb2_i2c_clk=2Ecommon=2Ehw,
>>> +		[CLK_R_APB1_IR]		=3D &r_apb1_ir_clk=2Ecommon=2Ehw,
>>> +		[CLK_IR]		=3D &ir_clk=2Ecommon=2Ehw,
>>> +	},
>>> +	=2Enum	=3D CLK_NUMBER_H616,
>>> };
>>>
>>> static struct ccu_reset_map sun50i_h6_r_ccu_resets[] =3D {
>>> @@ -165,6 +187,12 @@ static struct ccu_reset_map
>>> sun50i_h6_r_ccu_resets[] =3D {
>>> 	[RST_R_APB1_W1]		=3D  { 0x1ec, BIT(16) },
>>> };
>>>
>>> +static struct ccu_reset_map sun50i_h616_r_ccu_resets[] =3D {
>>> +	[RST_R_APB1_TWD]	=3D  { 0x12c, BIT(16) },
>>> +	[RST_R_APB2_I2C]	=3D  { 0x19c, BIT(16) },
>>> +	[RST_R_APB1_IR]		=3D  { 0x1cc, BIT(16) },
>>> +};
>>> +
>>> static const struct sunxi_ccu_desc sun50i_h6_r_ccu_desc =3D {
>>> 	=2Eccu_clks	=3D sun50i_h6_r_ccu_clks,
>>> 	=2Enum_ccu_clks	=3D ARRAY_SIZE(sun50i_h6_r_ccu_clks),
>>> @@ -175,6 +203,16 @@ static const struct sunxi_ccu_desc
>>> sun50i_h6_r_ccu_desc =3D {
>>> 	=2Enum_resets	=3D ARRAY_SIZE(sun50i_h6_r_ccu_resets),
>>> };
>>>
>>> +static const struct sunxi_ccu_desc sun50i_h616_r_ccu_desc =3D {
>>> +	=2Eccu_clks	=3D sun50i_h616_r_ccu_clks,
>>> +	=2Enum_ccu_clks	=3D ARRAY_SIZE(sun50i_h616_r_ccu_clks),
>>> +
>>> +	=2Ehw_clks	=3D &sun50i_h616_r_hw_clks,
>>> +
>>> +	=2Eresets		=3D sun50i_h616_r_ccu_resets,
>>> +	=2Enum_resets	=3D ARRAY_SIZE(sun50i_h616_r_ccu_resets),
>>> +};
>>> +
>>> static void __init sunxi_r_ccu_init(struct device_node *node,
>>> 				    const struct sunxi_ccu_desc *desc)
>>> {
>>> @@ -195,3 +233,10 @@ static void __init sun50i_h6_r_ccu_setup(struct
>>> device_node *node)
>>> }
>>> CLK_OF_DECLARE(sun50i_h6_r_ccu, "allwinner,sun50i-h6-r-ccu",
>>> 	       sun50i_h6_r_ccu_setup);
>>> +
>>> +static void __init sun50i_h616_r_ccu_setup(struct device_node
>*node)
>>> +{
>>> +	sunxi_r_ccu_init(node, &sun50i_h616_r_ccu_desc);
>>> +}
>>> +CLK_OF_DECLARE(sun50i_h616_r_ccu, "allwinner,sun50i-h616-r-ccu",
>>> +	       sun50i_h616_r_ccu_setup);
>>> diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-h6-r=2Eh
>>> b/drivers/clk/sunxi-ng/ccu-sun50i-h6-r=2Eh
>>> index 782117dc0b28=2E=2E128302696ca1 100644
>>> --- a/drivers/clk/sunxi-ng/ccu-sun50i-h6-r=2Eh
>>> +++ b/drivers/clk/sunxi-ng/ccu-sun50i-h6-r=2Eh
>>> @@ -14,6 +14,7 @@
>>>
>>> #define CLK_R_APB2	3
>>>
>>> -#define CLK_NUMBER	(CLK_W1 + 1)
>>> +#define CLK_NUMBER_H6	(CLK_W1 + 1)
>>> +#define CLK_NUMBER_H616	(CLK_IR + 1)
>>>
>>> #endif /* _CCU_SUN50I_H6_R_H */