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Date:   Thu, 03 Dec 2020 15:41:39 +0100
From:   Michael Walle <michael@walle.cc>
To:     Tudor.Ambarus@microchip.com
Cc:     linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org,
        miquel.raynal@bootlin.com, richard@nod.at, vigneshr@ti.com,
        boris.brezillon@collabora.com, stable@vger.kernel.org
Subject: Re: [PATCH v7 1/7] mtd: spi-nor: sst: fix BPn bits for the
 SST25VF064C
In-Reply-To: <fe37e295-9d74-160c-9b16-bbd5dcd5a638@microchip.com>
References: <20201202230040.14009-1-michael@walle.cc>
 <20201202230040.14009-2-michael@walle.cc>
 <fe37e295-9d74-160c-9b16-bbd5dcd5a638@microchip.com>
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Am 2020-12-03 15:40, schrieb Tudor.Ambarus@microchip.com:
> On 12/3/20 1:00 AM, Michael Walle wrote:
>> --- a/drivers/mtd/spi-nor/sst.c
>> +++ b/drivers/mtd/spi-nor/sst.c
>> @@ -18,7 +18,8 @@ static const struct flash_info sst_parts[] = {
>>                               SECT_4K | SST_WRITE) },
>>         { "sst25vf032b", INFO(0xbf254a, 0, 64 * 1024, 64,
>>                               SECT_4K | SST_WRITE) },
>> -       { "sst25vf064c", INFO(0xbf254b, 0, 64 * 1024, 128, SECT_4K) },
>> +       { "sst25vf064c", INFO(0xbf254b, 0, 64 * 1024, 128,
>> +                             SECT_4K | SPI_NOR_4BIT_BP) },
> 
> And I would put 1/7 after 4/7, so that I can set the locking flags
> in some order: SPI_NOR_HAS_LOCK | SPI_NOR_4BIT_BP. We first indicate
> that the flash supports locking, and then what kind of locking, BP3,
> and not the other way around.

If that patch shouldn't make it into stable, then yes. otherwise, I've
put these patches first to not cause merge conflicts.

-michael