Received: by 2002:a05:6a10:f347:0:0:0:0 with SMTP id d7csp619413pxu; Thu, 3 Dec 2020 08:34:55 -0800 (PST) X-Google-Smtp-Source: ABdhPJznj2q5lTBGFIW29ZAfQFJ79A57lzMs9LY47CLqLUiLomxHExTtm+USijySaTPhM+++cwUu X-Received: by 2002:a17:906:eb8d:: with SMTP id mh13mr3198730ejb.299.1607013295711; Thu, 03 Dec 2020 08:34:55 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1607013295; cv=none; d=google.com; s=arc-20160816; b=a3WACWjLiyLcYGt3pndrFG6kvuSyN2U2pKqlkE8IBNAosjypgHI/lMirTG9sjXyjKU XHIDYWcjqgZcFoY5K1bbTzNZkhkOzfXhBXPt69N3i3rRUjjSNRAug9Oeiu/Ro3nBczX1 xBjSh57tQH746kg0Ukf8yjEuA76Cs6rQ2ZUW0yn+2jpnjgUmWbKslFsg71fVSRvTqSnr Ds4rIxS9qsPmkPk3PQyINQXwsEdUxAvwGn2S+rF6j9wRwBozMM7wlMOolCjfIjr/rz8n dU0d04AQ67MLscZtUw3KrTNqSHYMuLQzoGmPlRbn6OimnNMf7J1xquCOkxMuDVdUXnDn TESw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=R18BnJGQhKpmO20tTgjY7h5EIqPjDxPHm/VryQ0fyrs=; b=orlf6riYxuyeijaIYWxUdTo2U7P8+baUWcuAKv5UddTD3tw1UFbnJ4vfGFGwL2fINu uy3LyPj+JQoih5Y/H8fcFtTdAkgf33o+jhMxM4uS2GQzemzzS5dANtLyJ+jXxwmklLUE TYiRHpc3X1CgZXRtNmSDktPyqkuN2WWFZJUfaOZRRH2oLK1bVh1ClU0b6kMY455kTLw2 re54WjKoXq7u31YXHGw7c4RLPbvQIyI18MPIaDZW76lLXJ5TeQyx3KUrIGfdh6vlqmK+ o5td/t9Nu2za2Dcax8FIGKtGV7v/vokFQreT4N99kaBfJE8ypNtbVzN/xeDlYBYFSjCh 9RFg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@walle.cc header.s=mail2016061301 header.b=r4ZXcE8a; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id r17si1352788ejd.551.2020.12.03.08.34.32; Thu, 03 Dec 2020 08:34:55 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@walle.cc header.s=mail2016061301 header.b=r4ZXcE8a; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731322AbgLCQbG (ORCPT + 99 others); Thu, 3 Dec 2020 11:31:06 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58980 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731279AbgLCQax (ORCPT ); Thu, 3 Dec 2020 11:30:53 -0500 Received: from ssl.serverraum.org (ssl.serverraum.org [IPv6:2a01:4f8:151:8464::1:2]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B3C62C061A51 for ; Thu, 3 Dec 2020 08:30:12 -0800 (PST) Received: from apollo.fritz.box (unknown [IPv6:2a02:810c:c200:2e91:6257:18ff:fec4:ca34]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-384) server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by ssl.serverraum.org (Postfix) with ESMTPSA id CDA4B23E5B; Thu, 3 Dec 2020 17:30:10 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=walle.cc; s=mail2016061301; t=1607013011; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=R18BnJGQhKpmO20tTgjY7h5EIqPjDxPHm/VryQ0fyrs=; b=r4ZXcE8aCkcqK2SZBj1XHMuQMwlChDNJkhaYSjZgqJKXq4aQKWoPtFHlYsLgK2TGUrcQac aUE6WB8prdzG/DJvAQCzbStTmBc1vBMZ2fwmpetcDnUxT/m8iOzdsYFwEcszStbKDu1Ge+ JRJQvn6V9apLU0gw3Gz5VrWkqQnGM9s= From: Michael Walle To: linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org Cc: Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , Tudor Ambarus , Boris Brezillon , Michael Walle Subject: [PATCH v8 3/7] mtd: spi-nor: atmel: remove global protection flag Date: Thu, 3 Dec 2020 17:29:55 +0100 Message-Id: <20201203162959.29589-4-michael@walle.cc> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201203162959.29589-1-michael@walle.cc> References: <20201203162959.29589-1-michael@walle.cc> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This is considered bad for the following reasons: (1) We only support the block protection with BPn bits for write protection. Not all Atmel parts support this. (2) Newly added flash chip will automatically inherit the "has locking" support and thus needs to explicitly tested. Better be opt-in instead of opt-out. (3) There are already supported flashes which doesn't support the locking scheme. So I assume this wasn't properly tested before adding that chip; which enforces my previous argument that locking support should be an opt-in. Remove the global flag and add individual flags to all flashes which supports BP locking. In particular the following flashes don't support the BP scheme: - AT26F004 - AT25SL321 - AT45DB081D Please note, that some flashes which are marked as SPI_NOR_HAS_LOCK just support Global Protection, i.e. not our supported block protection locking scheme. This is to keep backwards compatibility with the current "unlock all at boot" mechanism. In particular the following flashes doesn't have BP bits: - AT25DF041A - AT25DF321 - AT25DF321A - AT25DF641 - AT26DF081A - AT26DF161A - AT26DF321 Signed-off-by: Michael Walle Reviewed-by: Tudor Ambarus --- changes since v7: - none changes since v6: - none changes since v5: - none changes since v4: - none changes since v3/v2/v1: - there was no such version because this patch was bundled with another patch changes since RFC: - mention the flashes which just support the "Global Unprotect" in the commit message drivers/mtd/spi-nor/atmel.c | 28 +++++++++------------------- 1 file changed, 9 insertions(+), 19 deletions(-) diff --git a/drivers/mtd/spi-nor/atmel.c b/drivers/mtd/spi-nor/atmel.c index 3f5f21a473a6..49d392c6c8bc 100644 --- a/drivers/mtd/spi-nor/atmel.c +++ b/drivers/mtd/spi-nor/atmel.c @@ -10,37 +10,27 @@ static const struct flash_info atmel_parts[] = { /* Atmel -- some are (confusingly) marketed as "DataFlash" */ - { "at25fs010", INFO(0x1f6601, 0, 32 * 1024, 4, SECT_4K) }, - { "at25fs040", INFO(0x1f6604, 0, 64 * 1024, 8, SECT_4K) }, + { "at25fs010", INFO(0x1f6601, 0, 32 * 1024, 4, SECT_4K | SPI_NOR_HAS_LOCK) }, + { "at25fs040", INFO(0x1f6604, 0, 64 * 1024, 8, SECT_4K | SPI_NOR_HAS_LOCK) }, - { "at25df041a", INFO(0x1f4401, 0, 64 * 1024, 8, SECT_4K) }, - { "at25df321", INFO(0x1f4700, 0, 64 * 1024, 64, SECT_4K) }, - { "at25df321a", INFO(0x1f4701, 0, 64 * 1024, 64, SECT_4K) }, - { "at25df641", INFO(0x1f4800, 0, 64 * 1024, 128, SECT_4K) }, + { "at25df041a", INFO(0x1f4401, 0, 64 * 1024, 8, SECT_4K | SPI_NOR_HAS_LOCK) }, + { "at25df321", INFO(0x1f4700, 0, 64 * 1024, 64, SECT_4K | SPI_NOR_HAS_LOCK) }, + { "at25df321a", INFO(0x1f4701, 0, 64 * 1024, 64, SECT_4K | SPI_NOR_HAS_LOCK) }, + { "at25df641", INFO(0x1f4800, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_HAS_LOCK) }, { "at25sl321", INFO(0x1f4216, 0, 64 * 1024, 64, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, { "at26f004", INFO(0x1f0400, 0, 64 * 1024, 8, SECT_4K) }, - { "at26df081a", INFO(0x1f4501, 0, 64 * 1024, 16, SECT_4K) }, - { "at26df161a", INFO(0x1f4601, 0, 64 * 1024, 32, SECT_4K) }, - { "at26df321", INFO(0x1f4700, 0, 64 * 1024, 64, SECT_4K) }, + { "at26df081a", INFO(0x1f4501, 0, 64 * 1024, 16, SECT_4K | SPI_NOR_HAS_LOCK) }, + { "at26df161a", INFO(0x1f4601, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_HAS_LOCK) }, + { "at26df321", INFO(0x1f4700, 0, 64 * 1024, 64, SECT_4K | SPI_NOR_HAS_LOCK) }, { "at45db081d", INFO(0x1f2500, 0, 64 * 1024, 16, SECT_4K) }, }; -static void atmel_default_init(struct spi_nor *nor) -{ - nor->flags |= SNOR_F_HAS_LOCK; -} - -static const struct spi_nor_fixups atmel_fixups = { - .default_init = atmel_default_init, -}; - const struct spi_nor_manufacturer spi_nor_atmel = { .name = "atmel", .parts = atmel_parts, .nparts = ARRAY_SIZE(atmel_parts), - .fixups = &atmel_fixups, }; -- 2.20.1