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[23.128.96.18]) by mx.google.com with ESMTP id cw4si355055ejb.196.2020.12.03.16.14.51; Thu, 03 Dec 2020 16:15:15 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@chromium.org header.s=google header.b="YG7/BFHd"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=chromium.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2502088AbgLDALW (ORCPT + 99 others); Thu, 3 Dec 2020 19:11:22 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45824 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731928AbgLDALW (ORCPT ); Thu, 3 Dec 2020 19:11:22 -0500 Received: from mail-pg1-x544.google.com (mail-pg1-x544.google.com [IPv6:2607:f8b0:4864:20::544]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 33A5CC061A52 for ; Thu, 3 Dec 2020 16:10:42 -0800 (PST) Received: by mail-pg1-x544.google.com with SMTP id o5so2416121pgm.10 for ; Thu, 03 Dec 2020 16:10:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=mime-version:content-transfer-encoding:in-reply-to:references :subject:from:cc:to:date:message-id:user-agent; bh=4pKKFMfBLZOZ3sCLtJOcZ0LC1q6FIsFGdOapn0cj/sE=; b=YG7/BFHde8GeX7lx42RuXxFWd4/scS9eXfgkysdXbOefnXw2jtYTo0cjwW5BMdR3vC O21bBPedVmXiNUpaNTxJddYGeP9WwdxcU6KGBVuHmiI8IrVsOls5xwOUsBLE6vQYzpT2 hmydIfUrXeWnOUEU6hg2VZUGZeybW15x1AiZU= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:content-transfer-encoding :in-reply-to:references:subject:from:cc:to:date:message-id :user-agent; bh=4pKKFMfBLZOZ3sCLtJOcZ0LC1q6FIsFGdOapn0cj/sE=; b=pEAtyp/anadmI+9Yf9IBIoOLKeMvsrK2sv8QDNU9yHNkVEtL/YzWr3dC4L5f4hWduS SsFI6x84Yipb75JbO5o1SLwVXqWgLPy2iCNpuTV1L9HY329CFFf4jL01HsL+fS8a7ETD B2bxlmUeKMl3wZS5EjIP4+/AX5eiBPmk3xnQ6qutTCI9hmYvJ/+KPZ3iUkpg9T+gdLzI FflmfrNP0gj14hOnEcD2y+5tUZE6rvyAOPHTLoD/HwziV9cUeZWFxiu3S8d6C3EgVqmA hA679TziZPkz0lvnlQyjsUsY7wmqZkZbifI95SiYCSURzOFPId7UyyUV17NZIWKcpSiw t6Ww== X-Gm-Message-State: AOAM533n0RTnmsqvWMwvgtT3J+y37YyiBHH2Fy3Kh3NWlnlJiXHivZj8 bLk6EXl/1wXCTdxYfY2YSIBeXg== X-Received: by 2002:a63:6683:: with SMTP id a125mr5175488pgc.272.1607040641735; Thu, 03 Dec 2020 16:10:41 -0800 (PST) Received: from chromium.org ([2620:15c:202:201:3e52:82ff:fe6c:83ab]) by smtp.gmail.com with ESMTPSA id m26sm2802715pfo.123.2020.12.03.16.10.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Dec 2020 16:10:41 -0800 (PST) Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable In-Reply-To: References: <20201202214935.1114381-1-swboyd@chromium.org> <160695172591.2717324.17788035024164242534@swboyd.mtv.corp.google.com> <160695644776.2717324.633265815704005177@swboyd.mtv.corp.google.com> Subject: Re: [PATCH] spi: spi-geni-qcom: Use the new method of gpio CS control From: Stephen Boyd Cc: Alexandru M Stan , Mark Brown , linux-kernel , linux-arm-msm , linux-spi , Akash Asthana , Bjorn Andersson , Benson Leung , Enric Balletbo i Serra To: Doug Anderson Date: Thu, 03 Dec 2020 16:10:39 -0800 Message-ID: <160704063968.1580929.17834773484656581141@swboyd.mtv.corp.google.com> User-Agent: alot/0.9.1 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Quoting Doug Anderson (2020-12-03 12:06:10) > On Wed, Dec 2, 2020 at 4:47 PM Stephen Boyd wrote: > > > > And that is wrong. With even more investigation and Doug's eagle eyes it > > seems that the cros-ec driver is overriding the spi::mode to clear out > > the SPI_CS_HIGH bit that the spi core sets in there when using the gpio > > descriptors. I'll send a patch for cros-ec-spi shortly. >=20 > So do we need any coordinating here, are we OK w/ trogdor devices > being broken for a short period of time? >=20 > I think the device tree changes switching to use GPIO for chip select > is already queued in linux-next. That means if we land this patch > before the fix to cros_ec [1] then we'll end up in a broken state. > Would we be able to do some quick landing to get the cros-ec fix into > v5.10 and then target the SPI patch for 5.11? I don't think it really matters if the two patches meet up in linux-next or cros-ec is fast tracked, but it would be bad if this patch was merged without the cros-ec one. One option would be to apply the cros-ec fix to the spi tree along with this patch (or vice versa) so that a bisection hole isn't created. Or this patch can wait for a while until cros-ec is fixed. I'm not the maintainer here so it's really up to Mark and Enric/Benson. >=20 > [1] https://lore.kernel.org/r/20201203011649.1405292-2-swboyd@chromium.or= g/