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Subject: Re: [PATCH 5/5] clk: qcom: gcc: Add clock driver for SM8350
To:     Vinod Koul <vkoul@kernel.org>,
        Bjorn Andersson <bjorn.andersson@linaro.org>
Cc:     Stephen Boyd <sboyd@kernel.org>,
        Vivek Aknurwar <viveka@codeaurora.org>,
        Andy Gross <agross@kernel.org>,
        Michael Turquette <mturquette@baylibre.com>,
        Rob Herring <robh+dt@kernel.org>,
        linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org,
        devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
        Jeevan Shriram <jshriram@codeaurora.org>
References: <20201203070241.2648874-1-vkoul@kernel.org>
 <20201203070241.2648874-6-vkoul@kernel.org> <X8l9dRfo7qdRTAMe@builder.lan>
 <20201204043502.GJ8403@vkoul-mobl>
From:   Taniya Das <tdas@codeaurora.org>
Message-ID: <302cf18a-080d-a521-8c7a-39c265fbceb8@codeaurora.org>
Date:   Fri, 4 Dec 2020 14:20:55 +0530
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Hi Vinod,

On 12/4/2020 10:05 AM, Vinod Koul wrote:
> Hi Bjorn,
> 
> On 03-12-20, 18:06, Bjorn Andersson wrote:
>> On Thu 03 Dec 01:02 CST 2020, Vinod Koul wrote:
>>> diff --git a/drivers/clk/qcom/gcc-sm8350.c b/drivers/clk/qcom/gcc-sm8350.c
>> [..]
>>> +static int gcc_sm8350_probe(struct platform_device *pdev)
>>> +{
>>> +	struct regmap *regmap;
>>> +	int ret;
>>> +
>>> +	regmap = qcom_cc_map(pdev, &gcc_sm8350_desc);
>>> +	if (IS_ERR(regmap)) {
>>> +		dev_err(&pdev->dev, "Failed to map gcc registers\n");
>>> +		return PTR_ERR(regmap);
>>> +	}
>>> +
>>> +	ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks, ARRAY_SIZE(gcc_dfs_clocks));
>>> +	if (ret)
>>> +		return ret;
>>> +
>>> +	/* FORCE_MEM_CORE_ON for ufs phy ice core clocks */
>>> +	regmap_update_bits(regmap, gcc_ufs_phy_ice_core_clk.halt_reg, BIT(14), BIT(14));
>>> +
>>> +	/*
>>> +	 * Enable clocks required by the i2c-connected pm8008 regulators. Don't
>>> +	 * register them with the clock framework so that client requests are
>>> +	 * short-circuited before grabbing the enable/prepare locks. This
>>> +	 * prevents deadlocks between the clk/regulator frameworks.
>>> +	 *
>>> +	 *	gcc_qupv3_wrap_1_m_ahb_clk
>>> +	 *	gcc_qupv3_wrap_1_s_ahb_clk
>>> +	 *	gcc_qupv3_wrap1_s5_clk
>>> +	 */
>>
>> Isn't this a workaround inherited from the downstream control of
>> regulators from within the clock core? Does this still apply upstream?
> 
> Let me check on this bit...
> 
> Thanks
> 

No it should not apply.

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