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Date:   Fri, 4 Dec 2020 14:51:10 +0100
From:   Steen Hegelund <steen.hegelund@microchip.com>
To:     Russell King - ARM Linux admin <linux@armlinux.org.uk>
CC:     Andrew Lunn <andrew@lunn.ch>,
        Kishon Vijay Abraham I <kishon@ti.com>,
        Vinod Koul <vkoul@kernel.org>,
        <linux-arm-kernel@lists.infradead.org>,
        Alexandre Belloni <alexandre.belloni@bootlin.com>,
        Lars Povlsen <lars.povlsen@microchip.com>,
        Bjarni Jonasson <bjarni.jonasson@microchip.com>,
        Microchip UNG Driver List <UNGLinuxDriver@microchip.com>,
        <netdev@vger.kernel.org>, <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v8 3/4] phy: Add Sparx5 ethernet serdes PHY driver
Message-ID: <20201204135110.p5kdyvhxmuplao2u@mchp-dev-shegelun>
References: <20201203103015.3735373-1-steen.hegelund@microchip.com>
 <20201203103015.3735373-4-steen.hegelund@microchip.com>
 <20201203215253.GL2333853@lunn.ch>
 <20201203225232.GI1551@shell.armlinux.org.uk>
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Precedence: bulk

On 03.12.2020 22:52, Russell King - ARM Linux admin wrote:
>EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>
>On Thu, Dec 03, 2020 at 10:52:53PM +0100, Andrew Lunn wrote:
>> > +/* map from SD25G28 interface width to configuration value */
>> > +static u8 sd25g28_get_iw_setting(const u8 interface_width)
>> > +{
>> > +   switch (interface_width) {
>> > +   case 10: return 0;
>> > +   case 16: return 1;
>> > +   case 32: return 3;
>> > +   case 40: return 4;
>> > +   case 64: return 5;
>> > +   default:
>> > +           pr_err("%s: Illegal value %d for interface width\n",
>> > +                  __func__, interface_width);
>>
>> Please make use of dev_err(phy->dev, so we know which PHY has
>> configuration problems.
>>
>> > +static int sparx5_serdes_validate(struct phy *phy, enum phy_mode mode,
>> > +                                   int submode,
>> > +                                   union phy_configure_opts *opts)
>> > +{
>> > +   struct sparx5_serdes_macro *macro = phy_get_drvdata(phy);
>> > +   struct sparx5_serdes_private *priv = macro->priv;
>> > +   u32 value, analog_sd;
>> > +
>> > +   if (mode != PHY_MODE_ETHERNET)
>> > +           return -EINVAL;
>> > +
>> > +   switch (submode) {
>> > +   case PHY_INTERFACE_MODE_1000BASEX:
>> > +   case PHY_INTERFACE_MODE_SGMII:
>> > +   case PHY_INTERFACE_MODE_QSGMII:
>> > +   case PHY_INTERFACE_MODE_10GBASER:
>> > +           break;
>> > +   default:
>> > +           return -EINVAL;
>> > +   }
>> > +   if (macro->serdestype == SPX5_SDT_6G) {
>> > +           value = sdx5_rd(priv, SD6G_LANE_LANE_DF(macro->stpidx));
>> > +           analog_sd = SD6G_LANE_LANE_DF_PMA2PCS_RXEI_FILTERED_GET(value);
>> > +   } else if (macro->serdestype == SPX5_SDT_10G) {
>> > +           value = sdx5_rd(priv, SD10G_LANE_LANE_DF(macro->stpidx));
>> > +           analog_sd = SD10G_LANE_LANE_DF_PMA2PCS_RXEI_FILTERED_GET(value);
>> > +   } else {
>> > +           value = sdx5_rd(priv, SD25G_LANE_LANE_DE(macro->stpidx));
>> > +           analog_sd = SD25G_LANE_LANE_DE_LN_PMA_RXEI_GET(value);
>> > +   }
>> > +   /* Link up is when analog_sd == 0 */
>> > +   return analog_sd;
>> > +}
>
>You still have not Cc'd me on your patches. Please can you either:
>
>1) use get_maintainer.pl to find out whom you should be sending
>   your patches to
>or
>2) include me in your cc for this patch set as phylink maintainer in
>   your patch set so I can review your use of phylink.
>
>Consider your patches NAK'd until you send them to me so that I can
>review them.
>
>Thanks.

Hi Russell,

I will CC you on the next version of this series.  In reality I was
just asked by Vladimir Oltean to crosspost to netdev.  This is a
series for the Generic PHY subsystem.
Sorry about the confusion.
>
>--
>RMK's Patch system: https://www.armlinux.org.uk/developer/patches/
>FTTP is here! 40Mbps down 10Mbps up. Decent connectivity at last!

BR
Steen

---------------------------------------
Steen Hegelund
steen.hegelund@microchip.com